參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 164/176頁
文件大?。?/td> 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
164
Datasheet
Table 28. Synchronous Timing Reference Parameters
Timing
Number
Figure
Parameter
MIN
MAX
Unit
t
1
29
Setup time, CS* and DS* to C1 rising edge
15
ns
t
2
29
Setup time, R/W* to C1 rising edge
15
ns
t
3
29
Setup time, address valid to C1 rising edge
20
ns
t
4
29
C2 rising edge to data valid
60
ns
t
5
29
DTACK* low from C3 rising edge
1
30
ns
t
6
29
CS* and DS* trailing edge to data bus high-impedance
30
ns
t
7
29
CS* and DS* inactive between host accesses
10
ns
t
8
29
Hold time, R/W* after C3 rising edge
20
ns
t
9
29
Hold time, address valid after C3 rising edge
0
ns
t
10
30
Setup time, write data valid to C2 rising edge
0
ns
t
11
31
Setup time, DS* and DGRANT* to C1 rising edge
30
ns
t
12
31
Setup time, SVCACK* to DS* and DGRANT*
10
ns
t
13
30
Hold time, write data valid after C3 rising edge
0
ns
t
14
31
Propagation delay, DS* and DGRANT* to DPASS*
35
ns
t
15
32
33
Falling edge DMAREQ* after rising edge CLK (DMA write/read)
25
ns
t
16
32
33
Hold time, rising edge DMAREQ* after falling edge DMAACK*
(DMA write/read)
20
ns
t
17
32
Setup time, data valid before rising edge C3 (DMA write)
5
ns
t
18
32
33
Setup time, falling edge DMAACK* to falling edge C1 (DMA write/read)
10
ns
t
21
29
DTACK* active pull-up time
2
t
22
32
Hold time, data valid after rising edge C3 (DMA write)
5
t
23
33
Hold time, data valid after rising edge C1 (DMA read)
10
30
t
24
33
Data valid after falling edge C1 (DMA read)
25
t
25
33
Inactive time, DMAACK* (DMA read)
10
NOTES:
1. On host I/O cycles immediately following SVCACK* cycles and writes to EOSRR, DTACK* are delayed by 20 CLKs (1 ms @
20 MHz, 800 ns @ 25 MHz). On systems that do not use DTACK* to signal the end of the I/O cycle, wait states or some other
form of delay generation must be used to assure that the CD1284 is not accessed until after this time period.
2. DTACK* sources current (drives
‘
high
’
) until the voltage on the DTACK* line is approximately 1.5 V; then DTACK* enters the
‘
open-drain
’
(high-impedance) state.
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