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參數(shù)資料
| 型號(hào)： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個(gè)高速異步串行端口 |
| 文件頁(yè)數(shù)： | 145/176頁(yè) |
| 文件大?。?/td> | 2255K |
| 代理商： | CD1284 |
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IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
145
In the transmit direction, strings of three or more identical characters are recognized and
compressed. The running count of identical characters is kept in the RLCR. Once the sequence is
broken by a different character or the end of the transmit burst transfer, the count and a single copy
of the duplicated character are put in the FIFO.
In the receive direction, run-length codes can be received from the remote device. These codes are
recognized
‘
on the fly
’
as data flows from the FIFO through the holding register pipeline. A run-
length code is diverted to the RLCR. The subsequent character from the FIFO is duplicated (held in
PFHR1) while the RLCR decrements. Once the RLCR reaches
‘
0
’
, normal pipeline data movement
resumes. If run-length codes are being received by the parallel port but RLEen is not set, the codes
enter PFHR1 and PFHR2 as tagged data and cause interrupts to the host. The host must read the
tagged Holding register directly to remove the character from the pipeline and clear the tag.
This register is cleared by a device or FIFO reset.
7.7.17
Stale Data Timer Count Register
This register determines the period that signals stale data in the FIFO. The timer is used only in the
receive direction. Each time a new character is placed in the FIFO from the parallel port, the
SDTCR is reloaded from the SDTPR, and down-counting begins at the
‘
tick
’
rate. If the counter
reaches
‘
0
’
, the Stale bit (PFSR[2]) is set. If the amount of data available is greater than or equal to
one word, a DMA request is made to move all remaining whole words to the host with a DMA
transfer. Once the DMA transfer is complete, a single remaining character causes an interrupt to the
host to remove the character by reading PFHR2.
This register is cleared by a device or FIFO reset. Clearing it causes the Stale bit (PFSR[2]) to
become true.
7.7.18
Stale Data Timer Period Register
This register provides a user-defined period value for use as the timeout value of the stale data
timer (see SDTCR).
With a 25-MHz CLK input to the device, the resolution of this timer is 0.1 ms (with a maximum
value of 25.5 ms). The 25-MHz clock is divided by 250 to produce a 10-
μ
s intermediate clock for
this timer. A fixed, divide-by-ten prescaler produces 0.1-ms
‘
ticks
’
to the stale data timer. To ensure
accuracy for small timeout values, the prescaler is reset each time the stale data timer is reloaded.
(A user selection of 0.1-ms timeout results in a time delay between 0.09 and 0.1 ms.)
Register Name: SDTCR
Register Description: Stale Data Timer Count
Access: Read/Write
Bit 7
Bit 6
8-Bit Hex Address: 3D
Default Value: 00
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8-bit Stale Data Timer Count
Register Name: SDTPR
Register Description: Stale Data Timer Period
Access: Read/Write
Bit 7
Bit 6
8-Bit Hex Address: 3C
Default Value: 00
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
8-bit Stale Data Timeout Value
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