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參數(shù)資料
| 型號(hào)： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個(gè)高速異步串行端口 |
| 文件頁(yè)數(shù)： | 21/176頁(yè) |
| 文件大?。?/td> | 2255K |
| 代理商： | CD1284 |
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IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
21
DS*
77
I
ACTIVE-LOW DATA STROBE:
During an active I/O cycle, the input DS* strobes data
into On-Chip registers on write cycles or enables data onto the data bus during read
cycles. DS* is ignored during DMA operations.
BYTESWAP
82
I
BYTESWAP:
This input determines the byte order for 2-byte DMA transfers and for
writes to the DMA Buffer register. When BYTESWAP is
‘
1
’
, then Data Bus bits [15:8]
are driven with the byte transferred first on the parallel port bus. Data Bus bits [7:0] are
driven with the byte transferred second on the parallel port bus. When BYTESWAP is
‘
0
’
, the data order is reversed, bits [7:0] are driven with the byte transferred first and
bits [15:8] are driven with the byte transferred second.
DTACK*
75
AR
ACTIVE-LOW DATA TRANSFER ACKNOWLEDGE:
This output indicates: 1) when
the device completes the requested I/O operation, and, 2) when the current cycle can
finish. This signal can implement wait-state insertion for the local CPU. DTACK* does
not activate on DMA cycles.It is an active-release output, driving to a logic
‘
1
’
then
releasing to OD. DTACK* must be ties to external V
cc
through a pull-up resistor.
DMAREQ*
13
O
ACTIVE-LOW DMA REQUEST:
When the internal control bit DMAen is set, the output
DMAREQ* is asserted if internal FIFO conditions warrant a DMA transfer. DMAREQ*
is deasserted on the falling edge of DMAACK* when DMA transfers cannot continue
past the current transfer.
DMAACK*
12
I
ACTIVE-LOW DMA ACKNOWLEDGE:
This input is never asserted unless in
response to a DMAREQ* from the chip. DMAACK* is the only bus handshake signal
recognized during a DMA transfer. (CS* must be high whenever DMAACK* is
asserted). The direction of DMA transfer is determined by internal control bit DMAdir.
SVCREQR*
61
OD
ACTIVE-LOW SERVICE REQUEST RECEIVE:
This is an open-drain output and must
be tied to external V
through a pull-up resistor. When active, the device serial-
receive FIFO has either reached the programmed threshold or an exception condition
exists that requires CPU attention.
SVCACKR*
62
I
ACTIVE-LOW SERVICE ACKNOWLEDGE RECEIVE:
This input is driven low during
service acknowledge cycles to begin servicing a receive-service request. It must not
be driven active except in response to a receive-service request presented by the
device.
SVCREQT*
63
OD
ACTIVE-LOW SERVICE REQUEST TRANSMIT:
This is an open-drain output and
must be tied to external V
through a pull-up resistor. When active, the device serial
transmit FIFO or serial transmitter is empty and requires CPU attention.
SVCACKT*
64
I
ACTIVE-LOW SERVICE ACKNOWLEDGE TRANSMIT INPUT:
This input is driven
low during service acknowledge cycles to begin servicing a transmit-service request. It
must not be driven active except in response to a transmit-service request presented
by the device.
SVCREQP*
68
OD
ACTIVE-LOW SERVICE REQUEST PARALLEL:
This is an open-drain output and
must be tied to external V
through a pull-up resistor. SVCREQP* is not activated by
FIFO threshold or FIFO full/empty conditions.
SVCACKP*
69
I
ACTIVE-LOW SERVICE ACKNOWLEDGE PARALLEL:
This input cannot be driven
active except in response to a parallel service request presented by the device.
SVCREQM*
66
OD
ACTIVE-LOW SERVICE REQUEST STATUS
(Modem)
:
This is an open-drain output
that must be tied to external V
through a pull-up resistor. When active, a
programmed modem signal change occurs and requires CPU attention.
SVCACKM*
67
I
ACTIVE-LOW SERVICE ACKNOWLEDGE STATUS
(Modem)
:
This input is driven
low during service acknowledge cycles to begin servicing a modem-service request. It
must not be driven active except in response to a modem-service request presented
by the device.
DGRANT*
70
I
ACTIVE-LOW DAISY GRANT:
This input is driven active during service acknowledge
cycles to enable the daisy-chain function. This input, when qualified with DS* and a
valid service acknowledge (SVCACKR*, SVCACKT*, SVCACKM*, or SVCACKP*),
activates the CD1284 service-acknowledge cycle.
Table 1. Pin Descriptions
(Sheet 2 of 4)
Symbol
Pin No.
Type
Description
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