參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 108/176頁
文件大?。?/td> 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
108
Datasheet
7.0
Detailed Register Descriptions
This section presents a complete and detailed description of each register. Registers have two
formats: 1) full eight bits, where the entire content defines a single function; 2) the register is a
collection of bits, grouped singly or in multiples, defining a function. In the second format, the
descriptions divide the register into its component parts and describe the bits individually. The
order of register presentation corresponds to the register summary tables in
Chapter 4.0
.
7.1
Global Registers
7.1.1
Channel Access Register
The CAR provides access to individual channels within the CD1284. The least-significant two bits
of the register select one of the four channels. Before any operation that affects a channel, this
register must be loaded so that channel registers are available to the host. Bit 2 must always be
‘
0
’
.
Bits 7:3 are not used except during Poll-mode operation (see
Section 6.3
for details).
7.1.2
Global Firmware Revision Code Register
The GFRCR serves two purposes in the CD1284. First, it displays the revision number of the
firmware in the chip. When a revision to the CD1284 is required, the revision number of the
firmware is incremented by one. The revision code is 24 (hex) for the Revision D device, and 25
(hex) for the Revision E device.
Register Name: CAR
Register Description: Channel Access
Access: Read/Write
Bit 7
Poll
8-Bit Hex Address: 68
Default Value: XX
Bit 6
Poll
Bit 5
Poll
Bit 4
Poll
Bit 3
Poll
Bit 2
0
Bit 1
C1
Bit 0
C0
C1
C0
Channel Selected
0
0
Channel 0
0
1
Not used
1
0
Channel 2
1
1
Channel 3
Register Name: GFRCR
Register Description: Global Firmware Revision Code
Access: Read/Write
Bit 7
Bit 6
8-Bit Hex Address: 4F
Default Value: 25
Bit 5
Bit 4
Firmware Revision Code
Bit 3
Bit 2
Bit 1
Bit 0
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