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參數(shù)資料
| 型號： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口 |
| 文件頁數(shù)： | 74/176頁 |
| 文件大?。?/td> | 2255K |
| 代理商： | CD1284 |
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CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
74
Datasheet
P.O. Box 1331
Pascataway, NJ 08855-1331
USA
5.11.2
Bus Interface
DMA transfers are the preferred means of transferring data to/from the FIFO. However, it is also
possible to transfer data to/from the data pipeline by reading and writing the holding registers
directly through the PIO. DMA request and acknowledge handshake signals support transfers to/
from the 16-bit-wide DMABUF register. The direction of transfer is determined by the DMAdir bit
(PFCR[5]).
In the transmit direction, with DMAbufWe (PFCR[0]) set, the CPU can write 2 bytes at a time
directly to the DMABUF register. However, most applications are not concerned with speed on the
parallel port in the reverse direction and do not require 16-bit writes to the FIFO. The CPU must
avoid writing to these registers when they are already full or reading from them if they are empty.
The status bits in the HRSR indicate if the holding registers and the DMA buffer are full or empty.
When writing a block of data to the CD1284 (DMAbufWe is set to
‘
1
’
), the CPU can determine
how much data the FIFO can accommodate by reading the PFQR.
Should data become
‘
trapped
’
in the DMABUF register in the receive direction because of a failure
of the external DMA controller or because the external buffer area is full, it can either remain until
the DMA transfer can be resumed or the CPU can read the data directly from the DMA buffer.
Note:
The DMA buffer can only be read when DMAREQ* is active because data is not moved into the
DMABUF register until DMAREQ* is activated by the threshold logic or a timeout condition.
Once a DMA request is initiated by the CD1284, it is maintained until the last data transfer the
FIFO can accommodate occurs, or the CPU either clears DMAen or clears the FIFO and data-
transfer logic by setting FIFOres. In the transmit direction, the DMA request is removed by the
CD1284 when it determines that the FIFO is nearly full. (If RLEen is set, the pipeline does not
fully drain into the FIFO, but the logic does not factor that into the decision to conclude the DMA
transfer.)
In the receive direction, the DMA request is removed when there are not at least two more bytes
available to transfer or a tagged byte has moved into the data pipeline. In the latter case, an
interrupt is generated to the CPU (IntEn must be true) to remove the tagged data from the pipeline.
The quantity of data transferred within a single DMA request can significantly exceed the capacity
of the FIFO if RLEen is set, the parallel port is in ECP mode, and compressed data is being
transferred. This is because the FIFO always stores the data in compressed form. Since other
modes do not support RLE compression, the CPU should only set RLEen when the parallel port
interface is in ECP mode.
5.11.3
Parallel Port FIFO
The CD1284 has a dedicated 64-byte FIFO with counters to maintain the fill/empty pointer
addresses, logic to manage data transfers, automatic DMA handshake, and status interrupts to the
CPU. A simple register interface provides control over setting the direction of the pipeline,
initializing/resetting the DMA pointers, setting the DMA threshold, and so on. The FIFO
management logic responds to data-transfer requests from the dedicated IEEE 1284 parallel port
state machine.
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