參數(shù)資料
型號: CD1284
廠商: Intel Corp.
英文描述: IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述: 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù): 38/176頁
文件大小: 2255K
代理商: CD1284
CD1284
IEEE 1284-Compatible Parallel Interface Controller
38
Datasheet
For transmit and modem service-acknowledge cycles, the data in the lower three bits is redundant
to the software because the corresponding acknowledge has occurred. These bits are important in
the case of a serial receive-data service acknowledge because they provide an indication of whether
the request is for
good
data or exception data. They are important to the parallel port because they
indicate if the state-machine or data pipeline (or both) are requesting service.
The value contained in the upper five bits of the LIVR can be used for a number of purposes. The
primary purpose of the LIVR is as a source of a software vector used by the system as an index into
a interrupt dispatch table. However, systems that cannot use this or do not need it can use these bits
for any purpose. In multiple
CD1284 designs that use daisy-chaining, a logical value to place in
these bits is a chip identification number. This is detailed in the daisy-chaining description in
Section 5.3.4
.
Figure 5. Control Signal Generation
Table 14. Request-Type Bit Assignments
Bit 2
Bit 1
Bit 0
Request Type
0
0
0
Not used
0
0
1
Group 1: Modem signal change service request
0
1
0
Group 2: Transmit data service request
0
1
1
Group 3: Received good data service request
1
0
0
Parallel port state-machine requests service (refer to
Section 5.4
)
1
0
1
Parallel port data pipeline request service (refer to
Section 5.4
)
1
1
0
Both the parallel port state-machine and data pipeline request service (refer to
Section 5.4
)
1
1
1
Group 3: Received exception data service request
SVCACKR*
SVCACKT*
SVCACKM*
DGRANT*
CD1284
CS*
R/W*
DS*
AD[6:0]
DB[7:0]
SVCACKP*
CPU
ADDRESS
CPU I/O
CONTROL
ADDRESS
DECODE
LOGIC
CPU
DATA
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