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參數(shù)資料
| 型號： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口 |
| 文件頁數(shù)： | 171/176頁 |
| 文件大?。?/td> | 2255K |
| 代理商： | CD1284 |
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IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
171
11.0
Appendix A
11.1
Commonly Asked Questions
Using the SPR to Change Acknowledge Pulse Width in Compatible Mode
Some older hosts may require an acknowledge pulse width longer than the default 500 ns in
Compatible mode. The SPR can be used to change the pulse width in Compatible mode, but it
will also affect the transfer rate in the other modes. If the ACK* pulse width is extended 1
μ
s,
the transfer rates in other modes is slowed also. This should not be a concern as IEEE 1284-
compliant hosts work with an ACK* pulse width of 500 ns as specified in the IEEE 1284
specification (page 30). While non-IEEE 1284-compliant hosts cannot support any of the
advanced modes. In other words, if the host supports IEEE 1284 advanced modes (for example
ECP), then it also supports an ACK* pulse width of 500 ns in Compatible mode. If the host is
not IEEE 1284-compliant, then it does not support any of the advanced modes and therefore
the SPR is only used for compatibility mode.
BUSY/ACK* Timing Variations
The SPR cannot be used to support the Ack-while-Busy timing. If the SPR value is changed to
extend the ACK* pulse width, then the BUSY signal is extended as well. This means that the
CD1284 only supports the Compatible mode timing, Ack-in-Busy, as specified on pages 28
–
30 of the IEEE 1284 specification. Please read Section 6.3
“
Compatibility Mode
”
starting on
page 28. Based on this description of Compatibility mode, it is our belief that the Ack-in-Busy
timing on the peripheral-side interoperates with all existing hosts, including those that monitor
BUSY but not ACK*.
Device ID
At this time, Intel has no more information about device ID other than that is listed on page 52
of the IEEE 1284 specification. Contact Larry Stein, Chair of the IEEE 1284.3 working group,
at Far Point Communications (Fax: (805) 726-4438) for more information. Far Point
Communications also sells IEEE 1284-compliant ISA add-in boards for the PC. This board
can be useful for testing CD1284 applications.
Reversing the Channel with Data Remaining in the FIFO
The software must handle the situation where the host switches the direction of the parallel
interface from reverse to forward while data remains in the reverse FIFO. If this occurs then
the CD1284 produces a change of direction interrupt. When software detects this interrupt, it
must read the value in the PFQR (Parallel FIFO Quantity register) and use this value to
determine the bytes remaining in the FIFO. The software buffer pointer(s) must then be
adjusted by that amount so that the data in the FIFO can be resent when the direction is
reversed again. After the pointers are adjusted, the FIFO must be flushed (cleared) and the
direction of the FIFO must be changed to forward so that data may be received from the host.
RLE Data Count
Software can access the RLCR to obtain the current count for RLE data.
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