- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379802 > CD1284 (Intel Corp.) IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports PDF資料下載
參數(shù)資料
| 型號： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口 |
| 文件頁數(shù)： | 12/176頁 |
| 文件大小： | 2255K |
| 代理商： | CD1284 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
12
Datasheet
1.0
Overview
Ideal for printers, scanners, tape drives, set-top boxes, and data acquisition applications, the
CD1284 is a multi-function interface controller that implements a high-speed, multi-protocol
parallel port and two asynchronous serial ports. The device has both programmed I/O and DMA
operation (parallel port only), providing flexibility in local CPU interface design and high-speed
data transfers between the device and main memory.
The parallel port implements all modes of the
IEEE STD 1284 Standard Signaling Method for
Bidirectional Parallel Peripheral Interface for Personal Computers
specification, including EPP,
ECP, Reverse Byte, Reverse Nibble, and Compatible. Data transfer rates (up to 2 Mbytes/sec.) are
achievable on the parallel port when the device operates with a 25-MHz clock. The parallel port
data and control signals implement the IEEE STD 1284-defined Level-2 interface in drive type
(symmetrical), current capability (
±
14 mA), slew rate (0.4 V/ns), and 0.8 V hysteresis ( 2.0 V to
+
7.0 V protection is not implemented).
The two serial ports implement the standard asynchronous protocol. Functionally, the serial ports
are identical and register-set-compatible with the CD1400. The table below, shows the differences
between the CD1283 and CD1284.
Also included is a general-purpose port that provides eight bits of individual direction
programmable I/O that can be used for status and control of external functions.
Theory of Operation
The CD1284 is an efficient high-performance communications controller using an on-chip RISC
processor, which off-loads much of the work of sending and receiving data from the CPU.
Specifically for data communications applications, the RISC processor employs a high-
performance architecture developed by Intel. This internal CPU executes all instructions in one
clock cycle, and uses a windowed architecture to ensure zero-overhead context switching for each
type of internal interrupt. The processor is transparent to the user and does not require any
programming. It manages all serial data movement between the CPU and the two serial channels
and provides a flexible interrupt interface for the parallel channel. The parallel channel, being
separate and having its own intelligence, implements a very high-speed, peripheral-side parallel
data interface.
Each of the serial channels consist of separate 12- byte receive and transmit FIFOs. The parallel
channel has a single 64-byte FIFO to support the higher speeds obtainable on the parallel data port.
The serial receive FIFOs all have programmable thresholds to minimize interrupt latency
requirements. The parallel port FIFO has a programmable DMA threshold in both the receive and
transmit directions. The deep FIFOs reduce both the number of interrupt requests made of the CPU
and the time required to service them. The time required to service the requests is reduced by four
unique vectors that provide internal interrupt conditions. Whether it is receive, transmit, modem
signal change, or parallel port, the system spends less time determining the source of the
interrupt.The serial receive interrupt service time is further reduced by providing two types of
receive vectors: one for
‘
good
’
data and the other for
‘
exception
’
data. The CPU does not spend
Device
Number of
Serial Channels
Number of
Parallel Channels
CD1283
0
1
CD1284
2
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD13002 | NPN SILICON PLANAR EPITAXIAL, HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR |
| CD14538 | CMOS DUAL PRECISION MONOSTABLE MULTIVIBRATOR |
| CD14538BMS | CMOS Dual Precision Monostable Multivibrator |
| CD15B-15MB | CD105B |
| CD105B | CD105B |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12AFFM-QR8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12AMMM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12BFFA-LL7001 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12BFFA-QL8SP0 | 功能描述:CONN PLUG FMALE 12POS CRIMP 制造商:amphenol ltw 系列:X-Lok 包裝:散裝 零件狀態(tài):在售 連接器類型:插頭，母型插口 針腳數(shù):12（數(shù)據(jù)） 外殼尺寸 - 插件:C 外殼尺寸，MIL:- 安裝類型:自由懸掛 端接:壓接 緊固類型:推挽式 朝向:帶標(biāo)記 侵入防護(hù):IP68 - 防塵，防水 外殼材料，鍍層:聚酰胺（PA），尼龍，玻璃纖維增強(qiáng)型 觸頭鍍層:金 特性:后殼，應(yīng)力消除 電壓 - 額定:- 額定電流:5A 觸頭鍍層厚度:- 工作溫度:-20°C ~ 80°C 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。