參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 158/176頁
文件大?。?/td> 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
158
Datasheet
Note:
For synchronous systems, it is necessary to determine the clock cycle number so that interface
circuitry can stay in lock-step with the device. CLK numbers can be determined if RESET* is
released within the range t
a
–
t
b
; t
a
is defined as 10-ns minimum after the rising edge of the clock; t
b
is defined as 5-ns minimum before the next rising edge of the clock. If these conditions are met, the
cycle starting after the second rising edge is C1. See the synchronous timing diagrams for
additional information. Clock numbers are not important in asynchronous systems.
The following timing numbers are for the back-to-back asynchronous DMA timing diagrams.
t
25
26
Hold time, DMAACK* active (DMA read/write)
3 CLK
t
26
26
Delay, data valid after falling edge DMAACK* (DMA
read)
0.5 CLK
+
20
1.5 CLK
+
25
ns
t
27
26
Hold time, data valid after rising edge DMAACK* (DMA
read)
10
30
ns
t
28
26
28
Inactive time, DMAACK* (DMA read/write)
10
ns
t
29
26
28
Hold time, DMAREQ* rising edge after
DMAACK* falling edge (DMA read/write)
10
1 CLK
+
15
ns
t
30
28
Hold time, DMAACK* active (DMA write)
2.5 CLK
t
31
28
Delay, data valid after falling edge DMAACK* (DMA
write)
1.5 CLK
t
32
28
Hold time, data valid (DMA write)
3 CLK
+
10
ns
NOTES:
1. Timing numbers for RESET* and CLK in the table above are valid for both asynchronous and synchronous specifications.
The device operates on any clock with a 40
–
60 duty cycle or better.
2. On host-I/O cycles immediately following SVCACK* cycles and writes to EOSRR, DTACK* is delayed by 20 CLKs (1
μ
s @ 20
MHz, 800 ns @ 25 MHz). On systems that do not use DTACK* to signal the end of the I/O cycle, wait states or some other
form of delay generation must be used to assure that the CD1284 is not accessed until after this time period.
3. As TCLK increases, device performance decreases. A minimum clock frequency of 25 MHz is required to ensure
performance as specified. The recommended maximum TCLK is 1000 ns.
4. DTACK* sources current (drives
‘
high
’
) until the voltage on the DTACK* line is approximately 1.5 V; then DTACK* goes to the
‘
open-drain
’
(high-impedance) state.
Figure 20. Reset Timing
Table 27. Asynchronous Timing Reference Parameters
(Sheet 2 of 2)
Timing
Number
Figure
Parameter
MIN
MAX
Unit
t
1
V
CC
CLK
RESET*
t
a
t
b
C2
C1
C2
C1
C2
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