參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個(gè)高速異步串行端口
文件頁數(shù)： 143/176頁
文件大?。?/td> 2255K
代理商： CD1284
IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
143
These registers are cleared by a device or FIFO reset and marked as empty in HRSR. Any tagged
status is also cleared.
7.7.13
Parallel FIFO Quantity Register
This register maintains the quantity (or count) of either data bytes or space available in the parallel
FIFO. In the receive direction (DMAdir
=
0), PFQR counts data characters in the FIFO. In the
transmit direction (DMAdir
=
1), PFQR counts space available in the FIFO for additional
characters to transmit. FIFOres, together with the value of DMAdir, initialize PFQR to either x
’
00
(receive) or x
’
40 (transmit).
In either case, the PFQR indicates only the quantity of data or space available in the FIFO, and
does not include the data pipeline registers.
7.7.14
Parallel FIFO Status Register
This read-only register provides the current FIFO and data pipeline status. Host software should
examine these bits in response to pipeline interrupts or polling operations.
This register is not directly cleared by reset, but the individual bits reflect the status of other
registers.
Register Name: PFQR
Register Description: Parallel FIFO Quantity
Access: Read/Write
Bit 7
Bit 6
8-Bit Hex Address: 3A
Default Value: 00
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data or Space Available in FIFO
—
Max 0x40
Register Name: PFSR
Register Description: Parallel FIFO Status
Access: Read only
Bit 7
Bit 6
FFfull
FFempty
8-Bit Hex Address: 32
Default Value: 40
Bit 5
Timeout
Bit 4
HRtag
Bit 3
HRdata
Bit 2
Stale
Bit 1
Bit 0
DataErr
OneChar
Bit
Description
7
Parallel FIFO is Full:
If this bit is set, it indicates that the parallel FIFO is full.
6
Parallel FIFO is Empty:
If this bit is set, the parallel FIFO is empty.
5
Timeout:
This bit is set when Stale goes from false to true. In the receive direction, Timeout is delayed until
the FIFO is empty and all DMA cycles are complete (PFHR2 may or may not be full). Timeout is a pipeline
interrupt condition and must be cleared manually by the CPU. This is done by toggling ClrTO (PACR[3]) or by
a FIFO reset in PFCR.
4
Holding Register Tag:
This bit indicates that a tagged character is in either PFHR1, PFHR2, or both. If
enabled, this bit being set causes a host interrupt to be generated. The host should examine the HRSR to
determine the exact cause(s) of this bit being set.
3
Holding Register Data:
If this bit is set, it indicates that either PFHR1, PFHR2, or both contain data.
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