參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 112/176頁
文件大?。?/td> 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
112
Datasheet
Note:
This value does not have any effect on baud rate generation.
The time period generated by this register drives the receive timer and activates the
‘
no new data
’
and
‘
receive data timeout
’
interrupts. See the receiver operation discussion in
Chapter 5.0
for a
description of receiver timer functions.
7.1.9
Receive Interrupting Channel Register
See
Section 7.1.5 on page 109
, the description of the MICR, for details on the RICR.
7.1.10
Receive Interrupt Register
See
Section 7.1.6 on page 110
, the description of the MIR, for details on the RIR.
7.1.11
Service Request Register
The SVRR reflects the inverse of the state of the service request pins (SVCREQR*, SVCREQT*,
and SVCREQM*). Its primary use is in polled systems, and it allows system software to determine
what, if any, service requests are pending.
Register Name: RICR
Register Description: Receive Interrupting Channel
Access: Read/Write
8-Bit Hex Address: 44
Default Value: 00
7
6
5
4
3
2
1
0
X
X
X
X
C1
C0
X
X
Register Name: RIR
Register Description: Receive Interrupt
Access: Read/Write
Bit 7
Bit 6
RxIreq
Rxbusy
8-Bit Hex Address: 6B
Default Value: 18
Bit 5
Rxunfair
Bit 4
1
Bit 3
1
Bit 2
0
Bit 1
ch[1]
Bit 0
ch[0]
Register Name: SVRR
Register Description: Service Request
Access: Read only
Bit 7
DMAREQ
ExtM
8-Bit Hex Address: 67
Default Value: 00
Bit 6
Bit 5
ExtT
Bit 4
ExtR
Bit 3
SRP
Bit 2
SRM
Bit 1
SRT
Bit 0
SRR
Bit
Description
7
DMA Request Status:
‘
1
’
indicates request pending.
6
ExtM:
Reflects the current state of the external SVCREQM* signal.
5
ExtT:
Reflects the current state of the external SVCREQT* signal.
4
ExtR:
Reflects the current state of the external SVCREQR* signal.
3
Service Request Parallel:
‘
1
’
indicates request pending.
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