參數(shù)資料
型號(hào)： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個(gè)高速異步串行端口
文件頁數(shù)： 150/176頁
文件大?。?/td> 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
150
Datasheet
Setting the bits in this register enables the CD1284 to generate an interrupt
–
if SigCh (PCIER[4])
is set
–
when the selected signal changes from low-to-high (rising edge). Bits 7:4 are reserved and
must be written as zeros; they return zero when read. The settings in this register have no effect
(that is, a SigCh interrupt is not generated) unless the device is in Manual mode.
7.8.8
Output Value Register
This register controls output signals. In Manual mode, all signals are controlled by these register
settings. In Compatibility and EPP modes, PerBsy and PerClk are controlled by the internal
parallel port state machine, while AkDaRq, xFlag, and nDatAv are controlled by this register. In
ECP mode, the settings in this register have no effect.
7.8.9
Parallel Channel Interrupt Enable Register
7.8.10
Parallel Channel Interrupt Status Register
Register Name: OVR
Register Description: Output Value
Access: Write only
Bit 7
PerBsy
8-Bit Hex Address: 2B
Default Value: 48
Bit 6
PerClk
Bit 5
AkDaRq
Bit 4
xFlag
Bit 3
nDatAv
Bit 2
0
Bit 1
0
Bit 0
0
Bit
Description
7:6
Peripheral Busy and Peripheral Clock:
User-controlled in Manual mode only.
5
Acknowledge Data Request:
In Compatible mode, this signal is the PError (Peripheral Error) signal.
In EPP mode, this signal is auxiliary and is a user-defined signal (USER 1).
4
XFlag:
In Compatible mode, this signal is the SELCT (Select) signal.
In EPP mode, this signal is auxiliary and is a user-defined signal (USER 2).
3
Negative-true Data Available:
In Compatible mode, this signal is the nFault (negative-true fault) signal.
In EPP mode, this signal is auxiliary and is a user-defined signal (USER 3).
2:0
Reserved
: These bits must be written as
‘
0
’
.
Register Name: PCIER
Register Description: Parallel Channel Interrupt Enable
Access: Read/Write
Bit 7
Bit 6
0
TimEn
8-Bit Hex Address: 22
Default Value: 00
Bit 5
NegCh
Bit 4
SigCh
Bit 3
EPPAW
Bit 21
DirCh
Bit
Bit
nINIT
IDReq
Register Name: PCISR
Register Description: Parallel Channel Interrupt Status
Access: Read/Write
Bit 7
Bit 6
0
TimOvr
8-Bit Hex Address: 23
Default Value: 00
Bit 5
NegCh
Bit 4
SigCh
Bit 3
EPPAW
Bit 2
DirCh
Bit 1
IDReq
Bit 0
nINIT
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