參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 151/176頁
文件大?。?/td> 2255K
代理商： CD1284
IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
151
PCIER and PCISR provide control and status of interrupts generated by the parallel channel
control state machine. They have the same bit definitions. Each bit in the PCIER enables the
interrupt of the same type in the PCISR. A write of any value to the PCISR in response to an
interrupt request causes it to clear and the interrupt request is removed.
7.8.11
Parallel Configuration Register
This register controls the overall configuration of the parallel port, each of which is described in
IEEE 1284 format below.
Bit
Description
7
This bit must always be
‘
0
’
6
Timer Enable and Timer Over:
These two bits are for factory test purposes only and should never be
written.
5
Negotiation Change:
The state of this bit indicates that a change occurred in the negotiation status of the
port. The NSR indicates the new status of the parallel port.
4
Signal Change Enable:
This enable instructs the parallel port to generate an interrupt when any of the
signals specified by the ZDR or ODR change state as programmed. This interrupt is only generated during
Manual mode, however, it
cannot
be cleared by terminating Manual mode.
3
EPPAW:
The state of this bit indicates that the remote master has written an EPP address to the CD1284.
The new EPP address value is placed in the EAR.
2
Direction Change:
This bit indicates that the host-side parallel port changed the direction of the interface.
Generally, this is in response to a request made by the CD1284 through the RevRq bit (SCR[0]). DirCh
indicates that the direction was reversed through the defined protocol and the CD1284 can now send data to
the master.
1
ID Request:
The state of this bit indicates that the host has requested that the CD1284 send its ID data
string. The peripheral host sends the appropriate ID string (this is application dependent).
0
nINIT:
This interrupt is generated when an nINIT pulse is received while in Compatibility mode. The interrupt
occurs on the leading edge of the nINIT pulse.
Register Name: PCR
Register Description: Parallel Configuration
Access: R/W
8-Bit Hex Address: 20
Default Value: 00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ManMd
E1284
ETxfr
Ig_SEL
HTmrTst[1]
HTmrTst[0]
MMDir
ManOE
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