參數(shù)資料
型號(hào)： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個(gè)高速異步串行端口
文件頁數(shù)： 110/176頁
文件大?。?/td> 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
110
Datasheet
7.1.6
Modem Interrupt Register
The MIR, PIR, and TIR are used during Poll-mode operation of the CD1284. All three registers
provide the same type of information for each of the three service requests. The functions of
RxIreq, TxIreq, and MdIreq have identical meanings, as do the group Rxbusy, Txbusy, and
Mdbusy and the group Rxunfair, Txunfair, and Mdunfair. The least-significant two bits indicate the
number of the channel requesting service. Bits 4:2 are used internally by the CD1284 to set the
context of the service-acknowledge cycle. See the description of Poll-mode operations in
Chapter
5.0
for complete details.
Bit
Description
7:4
User defined.
3:2
Channel X:
When these bits are set to the values shown below, the channel number is defined.
1:0
User defined.
Register Name: MIR
Register Description: Modem Interrupt
Access: Read/Write
Bit 7
MdIreq
Mdbusy
8-Bit Hex Address: 69
Default Value: 08
Bit 6
Bit 5
Mdunfair
Bit 4
0
Bit 3
1
Bit 2
0
Bit 1
ch[1]
Bit 0
ch[0]
C1
C0
Channel Number
0
0
Channel 0
0
1
Undefined
1
0
Channel 2
1
1
Channel 3
Bit
Description
7
RxIreq, TxIreq, and MdIreq: These bits are set by the internal processor when service is required by a
channel. The bits are a direct reflection of the inverse state of the SVCREQ* pins and they are the active-high
output of the latch that drives the SVCREQ* pins. The bits can be scanned by the host to detect an active
service request. These bits are cleared by the internal processor at the beginning of the service-acknowledge
cycle (hardware-service acknowledge) or by the host software when the Poll-mode cycle is terminated.
6
Rxbusy, Txbusy, and Mdbusy: These bits are set by the internal processor and they remain set until the end of
the service-acknowledge cycle is indicated by either a write to the EOSRR (hardware-service acknowledge),
or cleared by the host software when the Poll-mode cycle is terminated. These bits signal the current state of
the service-acknowledge cycle. When cleared, the internal processor knows that it can assert another service
request of this type.
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