參數(shù)資料
型號： CD1284
廠商： Intel Corp.
英文描述： IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
中文描述： 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口
文件頁數(shù)： 100/176頁
文件大?。?/td> 2255K
代理商： CD1284
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
100
Datasheet
6.5.1
Software-Activated Service Examples (Poll)
The scanning loop for Poll-mode operation is shown in
Section 6.3
. Software activation of the
context switch is performed in the same manner, but termination of the service is done in two ways.
The first method is similar to the serial channel method and the second method can work well in
certain systems, but requires extra steps.
The first method follows the same basic procedure as the serial channels, but the termination
sequence requires only that the upper bit (PPIreq) of the PIR is cleared by the CPU. Since Fair
Share is not implemented on the parallel channel, there is no
‘
unfair
’
bit in the PIR; the
‘
busy
’
status is maintained by the MPU differently and is not maintained in the PIR.
Figure 19. Polling Flow Chart
HARDWARE RESET
TEST
SVRR
SERVICE NEGOTIATION
CHANGE
SET
SOFTWARE RESET
INITIALIZE DEVICE
TEST
PIR
TEST
PFSR
SERVICE DMA REQUEST
DMAREQ
POLL DEVICE AGAIN
SERVICE
SIGNAL
CHANGE
INTERRUPT
SERVICE
FIFO
CHANGE DIRECTION
RETURN ID TO HOST
RESET PRINTER
TEST
PCISR
TEST
NSR
TEST
SSR
TEST
PFSR
TEST
HRSR
= 00H
SRP SET
= 00H
Pipeline SET
PPort SET
DirCh
IDReq
nnt
NegCh SET
DataErr
SERVICE
ERROR
INTERRUPT
SERVICE
APPROPRIATE
HOLDING
REGISTER
OR
FF FULL
(receiving)
EMPTY
(transmiting)
OR
HR DATA
HR TAG
POLL DEVICE AGAIN
SigCh
NOTE:
It may not be necessary to poll the PFSR if
DMA requests are enabled. With DMA
requests enabled, the DMAREQ bit
(SVRR[7]) can be polled to determine
when a FIFO threshold is exceeded. If
DMA requests are disabled, the PFSR
must be polled to determine when to move
data to and from the FIFO. If DMA requests
are enabled, data must be read through the
DMABUF register; this requires a 16-bit
data bus.
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