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參數資料
| 型號： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口 |
| 文件頁數： | 73/176頁 |
| 文件大?。?/td> | 2255K |
| 代理商： | CD1284 |
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IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
73
The system clock is the external clock driving the CLK input of the CD1284. Three example baud
rate tables are provided at the end of
Section 6.7
on page . A sample program for automatically
deriving the baud rate clock selection and divisor is also provided in
Chapter 6.0
.
5.10
Serial Diagnostic Facilities
—
Loopback
The CD1284 provides the capability to perform internal loopback testing for both local and remote
loopback modes. Loopback mode is enabled by the LLM (Local Loopback mode) and RLM
(Remote Loopback mode) bits (COR2[4:3]).
In Local Loopback mode, the output of the transmitter bit engine is directly connected to the input
of the receiver bit engine; the input and output pins (TxD and RxD) are disconnected. The TxD
output is left in the mark condition so that remote equipment does not sense any line activity. Input
conditions on the RxD are ignored. All channel parameters and service-request functions are in
effect and operate normally. If enabled, special characters in the loopback data are detected and
acted upon and UNIX translations occur.
Remote Loopback mode causes the CD1284 to echo any received data back immediately to the
transmit output. This is done on a character-by-character basis rather than on a bit-by-bit basis. In
other words, characters are echoed once they are completely received and assembled. Received
data is not placed in the FIFO, thus no data is sent to the CPU. The received character is
retransmitted with parity and stop bit options as defined by COR1. Note, if the transmit baud rate is
lower than the receive baud rate, overrun errors and loss of data are likely to occur.
5.11
Parallel Port FIFO and Data Pipeline Overview
The parallel port within the CD1284 implements all modes defined for the
‘
slave
’
(peripheral) side
in the
IEEE STD 1284 Standard Signaling Method for a Bidirectional Parallel Peripheral Interface
for Personal Computers
. This specification defines four methods of performing bidirectional data
transfers between a computer system and a peripheral device, in addition to the generally accepted
unidirectional Centronics
-compatible mode. These modes include Compatibility mode, Reverse-
Nibble mode, Reverse-Byte mode, ECP (Extended Capabilities Port) with and without RLE (run
length encoding), and the EPP (enhanced parallel port).
The IEEE 1284-compliant parallel port consists of two major functional blocks:
A data pipeline that moves data between the parallel port and the CPU and includes a FIFO,
holding registers, DMA control, interrupt control logic.
A channel control state machine to perform all control and handshake generation on the
parallel port interface side of the device.
5.11.1
IEEE STD 1284 Protocols
The following sections discuss data movement within the pipeline for the various IEEE STD 1284
operating modes. For a complete description of these modes, refer to the IEEE STD 1284
specification; it is beyond the scope of this data book to give complete information on the
specification. A copy of the IEEE STD 1284 standard can be obtained from:
IEEE Standards Department
445 Hoes Lane
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