- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379802 > CD1284 (Intel Corp.) IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports PDF資料下載
參數(shù)資料
| 型號(hào)： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個(gè)高速異步串行端口 |
| 文件頁(yè)數(shù)： | 116/176頁(yè) |
| 文件大?。?/td> | 2255K |
| 代理商： | CD1284 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)當(dāng)前第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)
CD1284
—
IEEE 1284-Compatible Parallel Interface Controller
116
Datasheet
provides the character. It is not necessary to read either of these values. If the service acknowledge
is terminated without reading the exception status and data from the RDSR, the internal processor
updates the FIFO pointers as if the status/data were read. The same is true when only the status is
read. Overrun errors are an exception to this (see table below).
7.2.5
Receive Interrupt Vector Register
The value in this register is placed on the data bus, DB[7:0], when SVCACKR* is activated in
response to an active SVCREQR*. See
Section 7.4.6 on page 128
for more details on the LIVR.
Bit
Description
7
Timeout:
If the service request enable for timeout is set, this bit indicates that no data has been received
within the receive timeout period set by the RTPR after the last character was removed.
6:4
Special Character Detect: These three bits are encoded as follows:
NOTE:
No special character matching is performed if either a parity (PE) or framing (FE) error occur unless
CMOE is enabled by COR5[5].
3
Break:
Indicates that a break was detected.
2
Parity Error:
Indicates that a character was received with parity other than that programmed in COR1.
1
Framing Error:
Indicates that the character was received with a bad stop bit.
0
Overrun Error:
This bit is set if new data is received, but there is no space available in the FIFO and Holding
register. In this case, the character data is lost, and the overrun flag is applied to the last good data received
before the overrun occurred. Thus, the character read on the subsequent read from the RDSR is good data
and should not be discarded.
Register Name: RIVR
Register Description: Receive Interrupt Vector
Access: Read only
Bit 7
Bit 6
X
X
8-Bit Hex Address: 43
Default Value: 00
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
IT2
Bit 1
IT1
Bit 0
IT0
SCDet2
SCDet1
SCDet0
Status
0
0
0
None detected.
0
0
1
Special character 1 matched.
0
1
0
Special character 2 matched.
0
1
1
Special character 3 matched.
1
0
0
Special character 4 matched.
1
0
1
Not used.
1
1
0
End-of-break detected.
1
1
1
Range detect.
IT2
IT1
IT0
Description
0
0
0
No receive interrupt active.
0
0
1
Invalid.
0
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD13002 | NPN SILICON PLANAR EPITAXIAL, HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR |
| CD14538 | CMOS DUAL PRECISION MONOSTABLE MULTIVIBRATOR |
| CD14538BMS | CMOS Dual Precision Monostable Multivibrator |
| CD15B-15MB | CD105B |
| CD105B | CD105B |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12AFFM-QR8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12AMMM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12BFFA-LL7001 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:10 |
| CD-12BFFA-QL8SP0 | 功能描述:CONN PLUG FMALE 12POS CRIMP 制造商:amphenol ltw 系列:X-Lok 包裝:散裝 零件狀態(tài):在售 連接器類型:插頭，母型插口 針腳數(shù):12（數(shù)據(jù)） 外殼尺寸 - 插件:C 外殼尺寸，MIL:- 安裝類型:自由懸掛 端接:壓接 緊固類型:推挽式 朝向:帶標(biāo)記 侵入防護(hù):IP68 - 防塵，防水 外殼材料，鍍層:聚酰胺（PA），尼龍，玻璃纖維增強(qiáng)型 觸頭鍍層:金 特性:后殼，應(yīng)力消除 電壓 - 額定:- 額定電流:5A 觸頭鍍層厚度:- 工作溫度:-20°C ~ 80°C 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。