- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379802 > CD1284 (Intel Corp.) IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports PDF資料下載
參數(shù)資料
| 型號： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口 |
| 文件頁數(shù)： | 137/176頁 |
| 文件大?。?/td> | 2255K |
| 代理商： | CD1284 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁當前第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁
IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
137
7.7.2
DMA Buffer Data Register
—
High
7.7.3
DMA Buffer Data Register
—
Low
This 16-bit data register is used to buffer DMA data transfers to and from the CD1284. Under
normal operating conditions, this register is only accessed during a DMA data transfer cycle. If the
DMAbufWe (PFCR[0]) is set to
‘
1
’
and DMAdir (PFCR[5]) is set to
‘
1
’
, data may be transferred
from the host to the FIFO by directly writing to the DMABUF. The data automatically moves
forward into the FIFO through the Data Pipeline Holding registers. The user must ensure that the
FIFO has sufficient free space to accept the data before writing into the DMABUF.
The BYTESWAP pin determines the order of byte transfer from this register into the data pipeline.
If BYTESWAP is set to
‘
1
’
, data transferred on DB[15:8] is the first byte transferred into the data
pipeline and DB[7:0] is transferred second. If BYTESWAP is set to
‘
0
’
this sequence is reversed.
The same applies during data read during DMA transfers: if BYTESWAP is set to
‘
1
’
, data from
the data pipeline moves to the upper byte of DMABUF, the next byte moves into the lower byte.
Again, if BYTESWAP is set to
‘
0
’
, this sequence is reversed.
Bit
Description
7
DMA Write Error:
This bit is set if the DMA control logic has written to the DMA buffer when it already
contains data. It indicates that an invalid DMA transfer cycle occurred (a DMAACK* without a corresponding
DMAREQ*).
6
DMA Read Error:
As with bit 7, this bit indicates that DMA logic has performed a read from the DMA buffer
when there was no data in it. It indicates that an invalid DMA transfer cycle occurred.
5
Buffer Write Error:
This bit indicates that a system write to the DMA buffer occurred while it still contained
data.
4
Buffer Read Error:
This bit indicates that a system read from the DMA buffer occurred while it was empty.
3
Holding Register 1 Write Error:
This bit indicates that a system write to PFHR1 occurred while it still
contained data.
2
Holding Register 1 Read Error:
This bit indicates that a system read from PFHR1 occurred while it was
empty.
1
Holding Register 2 Write Error:
This bit indicates that a system write to PFHR2 occurred while it still
contained data.
0
Holding Register 2 Read Error:
This bit indicates that a system read from PFHR2 occurred while it was
empty.
Register Name: DMABUFH
Register Description: DMA Buffer Data Register, high
Access: Read/Write
Bit 7
Bit 6
15
14
8-Bit Hex Address: 30
Default Value: 00
Bit 5
13
Bit 4
12
Bit 3
11
Bit 2
10
Bit 1
9
Bit 0
8
Register Name: DMABUFL
Register Description: DMA Buffer Data Register, low
Access: Read/Write
Bit 7
Bit 6
7
6
8-Bit Hex Address: 30
Default Value: 00
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD13002 | NPN SILICON PLANAR EPITAXIAL, HIGH VOLTAGE FAST SWITCHING POWER TRANSISTOR |
| CD14538 | CMOS DUAL PRECISION MONOSTABLE MULTIVIBRATOR |
| CD14538BMS | CMOS Dual Precision Monostable Multivibrator |
| CD15B-15MB | CD105B |
| CD105B | CD105B |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD-12AFFM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
| CD-12AFFM-QR8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
| CD-12AMMM-QL8D01 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
| CD-12BFFA-LL7001 | 功能描述:MIDDLE 制造商:amphenol ltw 系列:* 零件狀態(tài):在售 標準包裝:10 |
| CD-12BFFA-QL8SP0 | 功能描述:CONN PLUG FMALE 12POS CRIMP 制造商:amphenol ltw 系列:X-Lok 包裝:散裝 零件狀態(tài):在售 連接器類型:插頭，母型插口 針腳數(shù):12（數(shù)據(jù)） 外殼尺寸 - 插件:C 外殼尺寸，MIL:- 安裝類型:自由懸掛 端接:壓接 緊固類型:推挽式 朝向:帶標記 侵入防護:IP68 - 防塵，防水 外殼材料，鍍層:聚酰胺（PA），尼龍，玻璃纖維增強型 觸頭鍍層:金 特性:后殼，應力消除 電壓 - 額定:- 額定電流:5A 觸頭鍍層厚度:- 工作溫度:-20°C ~ 80°C 標準包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復。