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參數資料
| 型號： | CD1284 |
| 廠商： | Intel Corp. |
| 英文描述： | IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports |
| 中文描述： | 符合IEEE 1284兼容并行接口控制器兩個高速異步串行端口 |
| 文件頁數： | 37/176頁 |
| 文件大小： | 2255K |
| 代理商： | CD1284 |
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IEEE 1284-Compatible Parallel Interface Controller
—
CD1284
Datasheet
37
However, software can easily change this by clearing the DMAen bit (PFCR[6]) at the start of
the interrupt service routine and resetting it at the end.
If SVCREQP* and DMAREQ* are logically OR
’
ed together, the service routine must start by
checking the SVRR to determine which signal is active.
SVCACKP* must not be activated in response to DMAREQ* and likewise, DMAACK* must
not be activated in response to SVCREQ*.
The DMAdir bit (PFCR[5]) can determine whether to write or read to/from the DMABUF
register.
The PFQR can determine how many reads of the 16-bit DMABUF register are necessary to
empty the pipeline. Note however, four must be added to the PFQR value, that number must
then be divided by two and truncated to the nearest integer (to account for the extra four bytes
in the two holding registers and the 16-bit DMABUF register, as well as 16-bit reads instead of
8-bit reads).
5.3.2.1
Hardware-Activated Context Switch
—
Serial Channels
The internal register manipulation involved in a context switch can be forced by SVCACK*
(Service Acknowledge input pins on the CD1284). There is one SVCACK* for each service
request type: SVCACKR* for receive service requests, SVCACKT* for transmit service requests,
and SVCACKM* for modem signal-change service requests. Each of these inputs is a special-case
chip select. These cause the MPU to set up the CD1284 for servicing that particular service request
type for the requesting channel.
Note that the CS* input is not activated on service-acknowledge cycles. Instead, the appropriate
SVCACK* input and the DGRANT* inputs are used. Later in this section, DGRANT* is discussed
in a description about daisy-chaining the CD1284 with one or more CD1400s.
Figure 5
shows a
generalized logic diagram of the hardware interface to the SVCACK* inputs. For a service
acknowledge, one of the SVCACK* address locations is accessed instead of the CS* location.
To the CPU, the service-acknowledge cycle is a read cycle. The data that the CD1284 places on the
bus for an SVCACK* during the read cycle are the contents of the appropriate Interrupt Vector
register (RIVR, TIVR or MIVR). These IVRs are associated with the active service-acknowledge
input (SVCACKR*, SVCACKT*, or SVCACKM*). The upper five bits of the IVR are whatever
was previously loaded into the LIVR by the CPU. The lower three bits are supplied by the CD1284
and indicate the type of interrupt (vector).
When the CD1284 is ready to post a service request for a serial channel, it copies the upper five bits
of the LIVR into the appropriate vector register (RIVR, TIVR, MIVR), then places the request type
vector in the lower three bits.
Table 14
shows the assignment of the request type bits.
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