參數(shù)資料
型號(hào)： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 95/110頁(yè)
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
91
Lucent Technologies Inc.
Register Structure
(continued)
Parameter/Control Registers
(continued)
Framer Idle Code Register (PR12)
These 8 bits are transmitted in each time slot when the transmit channel squelch command is enabled.
Table 68. Framer Line Idle Code Register (PR12)
CHI Common Control Register (PR13)
These bits define the common attributes of the CHI for both DX and DR.
Table 69. CHI Common Control Register (PR13)
CHI Transmit Control Register (PR14)
Table 70. CHI Transmit Control Register (PR14)
Bits
0—7
Description
Line Idle Code 0—7 (IC0—IC7) (Default = 01111111).
Bits
0—2
Description
CHI DX Bit Offset (XOFF0—XOFF2).
These 3 bits define the bit offset from FS for each transmit time
slot. CMS = 0, the offset is the number of CLKXR clock periods by which the first bit is delayed from FS.
CMS = 1, the offset is twice (2X) the number of CLKXR clock periods by which the first bit is delayed
from FS.
Highway Enable (HWYEN).
A 1 in this bit position enables transmission to the concentration highway.
This allows the T7230A to be fully configured before transmission to the highway. A 0 forces the idle code
as defined in PR12, to be transmitted to the line in all payload time slots and the DX pin is forced to a
high-impedance state for all CHI transmitted time slots.
CHI DR Bit Offset (ROFF0—ROFF2).
These 3 bits define the bit offset from FS for each received time
slot. CMS = 0, the offset is the number of CLKXR clock periods by which the first bit is delayed from FS.
CMS = 1, the offset is twice (2X) the number of CLKXR clock periods by which the first bit is delayed
from FS.
Frame Clock Edge (FE).
A 0 (1) enables the falling (rising) edge of CLKXR to latch in the frame syn-
chronization signal, FS.
3
4—6
7
Bits
0—5
Description
Transmit Byte Offset (XBYOFF0—XBYOFF5).
These 6 bits define the byte offset from FS to the begin-
ning of the next transmit CHI frame on DX.
Transmitter Clock Edge (XCE).
A 1 (0) enables the rising (falling) edge of CLKXR to clock out data on
DX.
Transmit Least Significant Bit First (XLBIT).
A 0 forces the most significant bit of each time slot (bit 0)
as the most significant bit of the time slot. A 1 forces the least significant bit of each time (bit 7) as the
most significant bit of the time slot.
6
7
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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