參數(shù)資料
型號(hào): T7230A
廠(chǎng)商: Lineage Power
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 49/110頁(yè)
文件大小: 752K
代理商: T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
45
Lucent Technologies Inc.
CEPT Time Slot 0 FAS/NOT FAS Control Bits
FAS/NOT FAS Si- and E-Bit Source
The Si bit can be used as an 8 kbits/s data link to and from the remote end, or in the CRC-4 mode, it is used to pro-
vide added protection against false frame alignment. In the LFA state, receive Si = 1 in the status registers. The
sources for the Si bit that are transmitted to the line by order of priority are:
1.
Non-CRC-4 mode: the SiF control bit in bit 1 of all FAS frames and the SiNF control bit in bit 1 of all NOT FAS
frames. This is the default transmission mode.
2.
The CHI system interface. This option requires the received system data (DRA or DRB) to maintain a biframe
alignment pattern where frames containing Si bit information for the NOT FAS frames have bit 2 of time slot 0
in the binary 1 state followed by frames containing Si bit information for the FAS frames have bit 2 of time slot 0
in the binary 0 state. This ensures the proper alignment of the Si received system data to the transmit line Si
data. Whenever this requirement is not met by the system, the T7230A transmit framer will enter a loss of
biframe alignment condition (indication is given in the status registers) and then search for the pattern; in the
loss of biframe alignment state, transmitted line data is corrupted (only when the system interface is sourcing
stand or Si data). When the transmit framer locates a new biframe alignment pattern, an indication is given in
the status registers and the transmit framer resumes normal operations.
3.
A secondary option assumes that every time slot 0 of DRA (or DRB) consists of the NOT FAS Sa bits (every
two frames contain the same NOTFAS data in time slot 0). The transmit framer transmits the Sa bits transpar-
ently from either the even or odd frame of DRA. The choice of even or odd frames is arbitrary.
4.
CRC-4 mode:
1
A. If not automatically transmitting E bits to the distant end (default):
a. Bit 1 of frame 13 = the SiF control bit, and bit 1 of frame 15 = the SiNF control bit.
B. If automatically transmitting E bits (ATERCRCE = 1) to the line interface, the Si bits in frames 13 and 15
are controlled by the state of the receive framer such that:
a.
One transmitted E bit is set to 0 by the transmit framer, as described in ITU Rec. G.704 Section
2.3.3.4, for each received errored CRC-4 submultiframe detected by the receive framer,
b.
As described in ITU Rec. G.704 Section 2.3.3.4, both E bits are set to 0 while in a received loss of
CRC-4 multiframe alignment state
2
.
c.
When the 400 ms timer is enabled
3
and this 400 ms timer has expired, as described in ITU Rec. G.706
Section B.2.2, both E bits are set to 0 for the duration of the loss of CRC-4 multiframe alignment state
3
.
Otherwise, the E bits are transmitted to the line in the 1 state.
1.
The receive E-bit processor will halt the monitoring of received E-bits during loss of CRC-4 multiframe alignment.
2.
Whenever loss of frame alignment occurs, then loss of CRC-4 multiframe alignment is forced. Once frame alignment is established, then and
only then is the search for CRC-4 multiframe alignment initiated. The receiver framer unit, when programmed for CRC-4, can be in a state of
LFA and LMFA or LMFA only, but can never be in a LFA only state.
3.
The CRC-4 interworking algorithm can only be enabled if and only if the receive framer is in the CRC-4 mode.
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