參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 69/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
65
Lucent Technologies Inc.
Phase-Lock Loop Circuit
The block diagram of the T7230A phase detector circuitry is shown in Figure 18. The T7230A uses elastic store
buffers (two frames) to accommodate the transfer of data from the system interface clock rate of 2.048 Mbits/s to
the line interface clock rate of either 1.544 Mbits/s or 2.048 Mbits/s.The transmit line side of the T7230A does not
have any mechanism to monitor data overruns or underruns (slips) in its elastic store buffer. This interface relies on
the requirement that the PLLCK clock signal (variable) is phase-locked to the CLKXR clock signal (reference).
When this requirement is not met, uncontrolled slips may occur in the transmit elastic store buffer that would result
in corrupted data and no indication will be given. Typically, a variable clock oscillator (VCXO) is used to drive the
PLLCK signal. The T7230A provides a phase error signal (EPLL) that can be used to control the VCXO. The EPLL
signal is generated by monitoring the divided-down PLLCK (DPLLCK) and CLKXR (DCLKXR) signals and using
the DCLKXR signal as a reference to determine the phase difference between DLKCXR and DPLLCK. While
DCLKXR and DPLLCK are phase-locked, the EPLL signal is in a high-impedance state. If the T7230A determines
that the VCXO needs adjusting, EPLL is driven to either 5 V or 0 V. An RC circuit (typically, R = 1 k
and C =
0.1
μ
F) is used to filter the EPPL signal for the VCXO.
The receive line elastic store buffer contains circuitry that monitors the read and write pointers for potential data
overruns and underruns (slips) conditions. Whenever this slip circuitry determines that a slip may occur in the
receive elastic store buffer, it will adjust the read pointer such that a controlled slip is performed. The controlled slip
is implemented by dropping or repeating a complete frame at the frame boundaries. The occurrence of controlled
slips in the receive elastic store is indicated in the status registers.
The T7230A can be programmed to use the receive line signal as the reference and the CLKXR signal as the vari-
able signal. This requires RLCK and PLLCK be tied to the RLCK signal and the PLLREF bit in the parameter regis-
ter to be programmed to 1. In this mode, the T7230A acts as a master timing source and is capable of generating
the system frame synchronization signal through the OFS output pin.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明:
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