參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 93/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
89
Lucent Technologies Inc.
Register Structure
(continued)
Parameter/Control Registers
(continued)
Signaling Mode Register (PR10)
Table 66. Signaling Mode Register (PR10)
Bits
0
Description
Transparent Signaling (TSIG).
A 0 enables signaling information to be inserted into and extracted from
the data stream. The signaling source is either the signaling registers or the system data (in the associ-
ated signaling mode). In DS1 modes, the choice of data or voice channels assignment for each channel
is a function of the programming of the F and G bits in the transmit signaling registers. A 1 (the default
mode) enables data to pass through the device transparently. All channels are treated as data channels.
Stomp Mode (STOMP).
A 1 enables the receive signaling circuit to replace (in those time slots pro-
grammed for signaling) all signaling bits (in the receive line bit stream) with a 1, after extracting the valid
signaling information. A 0 allows the received signaling bits to pass through the receive signaling circuit
unmodified.
Associated Signaling Mode (ASM).
A 1 enables the associate signaling mode that configures the CHI
to carry both data and its associated signaling information for a particular channel. Enabling this mode
must be in conjunction with the programming of the CHI data rate to 4.048 Mbits/s. Each channel con-
sists of 16 bits where 8 bits are data and the remaining 8 bits are signaling information
Channel Signaling Suppression or Nine-State Signaling (CCS_9ST).
DS1 SLC-96: A 1 enables the nine-state signaling mode.
CEPT: A 1 enables the received signaling circuit substitute of the signaling combination of
ABCD = 0000 to ABCD = 1111.
Message-Oriented Signaling or Common Channel Signaling (MOS_CCS).
DS1: A 1 enables the channel 24 message-oriented signaling mode.
CEPT: A 1 enables the time slot 16 common channel signaling mode.
IRSM/TSRFGE Mode (IRSM).
A 1 enables the CEPT IRSM mode in time slot 0. DS1 formats and ASM
= 1: A 1 enables the transmit signaling register F and G bits to define the robbed-bit signaling format
while the ABCD bit information is extracted from the CHI interface. The F and G bits are copied to the
receive signaling block and are used to extract the signaling information from the receive line.
Framer Data (FRMD).
A 0 enables the divided down signal of PLLCK and CLKXR onto the DPLLCK
and DCLKXR output pins, respectively. A 1 forces receive line data and receive line frame synchroniza-
tion signals onto the DPLLCK and DCLKXR output pins, respectively. Enabling this mode assumes an
application that does not require the divided down PLLCK and CLKXR signals.
Framer Factory Test (FFT2)
. This bit must always be 0.
1
2
3
4
5
6
7
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
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T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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