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參數(shù)資料
| 型號： | T7230A |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 62/110頁 |
| 文件大?。?/td> | 752K |
| 代理商： | T7230A |
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Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
58
Lucent Technologies Inc.
Alarms and Performance Monitoring
(continued)
Transmit Line Test Patterns
The transmit framer can be programmed to transmit various test patterns. These test patterns, when enabled, over-
write the receive CHI data. The test pattern is:
1.
The unframed-AIS pattern consists of a continuous bit stream of 1s (. . . 111111 . . .).
2.
The unframed-auxiliary pattern consists of a continuous bit stream of alternating 1s and 0s (. . . 10101010).
3.
The framed-AIS (high-density) test pattern consists of:
A. A continuous 1 pattern in time slots.
B. Valid framing bits.
C. CRC bits resulting from the pattern.
4.
The framed walking-one (low-density) test signal consists of (T1 only):
A. A repeating one-in-eight (00000001) pattern resulting in a walking-one pattern after the F bit is inserted.
B. Valid framing bits inserting into the pattern.
C. Valid transmit facility data link (XFDL) bit information (ESF).
D. CRC-6 bits that result from the above pattern in the payload bits (if ESF enabled).
5.
The quasi-random test signal consists of:
A. A pattern produced by means of a 20-stage shift register with feedback taken from the 17th and 20th
stages via an exclusive OR gate to the first stage. The output is taken from the 20th stage and is forced to
a 1 state whenever the next 14 stages (19 through 6) are all 0. The pattern length is 1,048,575 or 2
20
– 1
bits. This signal is described in detail in AT&T Technical Reference 62411 [5] Appendix.
B. Valid framing bits.
C. Valid transmit facility data link (XFDL) bit information (ESF).
6.
The pseudorandom test pattern consists of:
A. A 2
15
– 1 pattern inserted in the entire payload (time slots 1—31), as described by ITU Rec. 0.151 and
illustrated in Figure 15.
B. Valid FAS and NOT FAS* time slots.
C. Valid CRC-4 bits.
7.
The idle code test pattern consists of:
A. The programmable idle code in time slots 1—31.
B. Valid FAS and NOT FAS* time slots.
C. Valid CRC bits.
*The transmit Si, E, A, and Sa4 through Sa8 bits are transmitted as defined in the control registers.
5-3915(F)r.3
Figure 15. 15-Stage Shift Register Used to Generate the Pseudorandom Signal
D
A
B
C
A
B
0
1
1
0
0
0
1
1
C
0
1
0
1
XOR
D-TYPE FLIP-FLOPS
TRUTH TABLE FOR THE XOR GATE
#1
D
D
#2
#3
D
#13
D
D
#14
#15
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