參數(shù)資料
型號(hào)： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 5/110頁(yè)
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
Features
I
Framing formats
— DS1 extended superframe (ESF)
— DS1 superframe (SF): D4;
T1DM DDS; T1DM DDS with FDL access
— DS1 independent transmit and receive framing
modes when using the ESF and D4 formats
— ITU-CEPT 2.048 Mbits/s basic frame
— ITU-CEPT selectable CRC-4 multiframe align-
ment algorithms: 100 ms timer; 400 ms inter-
working timer. Optional basic frame resyn-
chronization with >915 CRC-4 checksum errors
— ITU-CEPT automatic received E-bit processing;
optional detection of permanently received
E bit = 0 events in a five-second interval
— Selectable automatic transmission for E bit to the
line
Line codes
— DS1: alternate mark inversion (AMI);
binary eight zero code suppression (B8ZS);
per-channel zero code suppression (ZCS)
— DS1 independent transmit and receive path line
code formats when using AMI/ZCS and B8ZS
coding
— ITU-CEPT: AMI; high-density bipolar 3 (HDB3)
encoding and decoding double bipolar violation
monitoring with optional monitoring of 4-bit inter-
val without positive or negative pulses error indi-
cation
Signaling
— DS1: extended superframe 2-state, 4-state, and
16-state per-channel robbed bit
— DS1: D4 superframe 2-state and 4-state
per-channel robbed bit
— DS1:
SLC
-96 superframe 2-state, 4-state, and
9-state per-channel robbed bit
— DS1: channel 24 message-oriented signaling
— ITU-CEPT: common channel signaling (CCS)
— ITU-CEPT: channel associated signaling (CAS)
— ITU-CEPT: international remote switching
module (IRMS)
— Transparent (all data channels)
Programmable elastic store buffer depth
— Two-frame (64-byte) default
— 6-byte option
Digital phase comparator with selectable reference
signal using either the system clock or the receive
line clock
SLC
-96;
I
I
I
I
I
Alarm reporting and performance monitoring
— ANSI and AT&T standard error checking
— Programmable ANSI yellow alarm processing
— ITU standard error checking
— Selectable interrupts enables
— Error counters: Bipolar violations
Errored frame alignment signals
Errored CRC checksum block
— Errored seconds, severely errored seconds, and
unavailable seconds processing
— Programmable automatic and on-demand alarm
signal generation
— Multiple loopback modes
— Selectable test patterns for line transmission
— Programmable squelch and idle codes
System interface
— One frame synchronization input signal
— One system interface clock
— Programmable clock edge for latching frame
synchronization signal
— 2.048 Mbits/s, 2.048 MHz concentration highway
interface (CHI) default mode
— Optional 2.048 Mbits/s, 4.096 MHz 32 time slots
mode
— Optional 4.096 Mbits/s, 4.096 MHz 32 time slots
mode
— Optional 4.096 Mbits/s, 8.196 MHz 32 time slots
mode
— Programmable bit and byte offset
— Programmable clock edge for receive and trans-
mit data
— Programmable CHI master mode for the genera-
tion of the CHI FS from internal logic with timing
derived from the receive line clock signal
Selectable microprocessor interface
— 16 MHz read and write access with no wait-
states
— Programmable
Intel
* and
modes
— Demultiplexed address and data bus
— Directly addressable internal registers
Hardware reset
Software reset
3-statable outputs
I
I
Motorola
interface
I
I
I
*
Intel
Motorola
is a registered trademark of Intel Corporation.
is a registered trademark of Motorola, Inc.
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參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
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T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
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