參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 92/110頁
文件大小： 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
88
Lucent Technologies Inc.
Register Structure
(continued)
Parameter/Control Registers
(continued)
System Interface Control Register (PR9)
Table 65. Facility Alarm Interrupt Enable Register (PR9)
Bits
0—2
Description
Stuffed Time Slots (STS0—STS2).
In DS1 modes only:
012
000: SDDDSDDDSDDDSDDDSDDDSDDDSDDDSDDD
001: DSDDDSDDDSDDDSDDDSDDDSDDDSDDDSDD
010: DDSDDDSDDDSDDDSDDDSDDDSDDDSDDDSD
011: DDDSDDDSDDDSDDDSDDDSDDDSDDDSDDDS
1XX: DDDDDDDDDDDDDDDDDDDDDDDDSSSSSSSS (Default mode)
012
000: Sa4 = FDL
001: Sa5 = FDL
010: Sa6 = FDL
011: Sa7 = FDL
100: Sa8 = FDL
Phase-Lock Loop Reference (PLLREF).
A 0 enables the use of the clock signal CLKXR as the refer-
ence signal and PLLCK as the variable signal internal phase-lock loop circuit. The EPLL signal is con-
nected to the VCXO circuit that produces the PLLCK signal.
A 1 enables the use of the clock signal PLLCK as the reference signal and CLKXR as the variable signal
internal phase-lock loop circuit. The EPLL signal is connected to the VCXO circuit that produces the
CLKXR signal. This mode can be used in applications where the receive line clock is the reference signal;
the receive clock signal must be connected to the RLCK input (as normal) and the PLLCK input. The
T7230A is the “master” clock source of the system in this mode. In the master mode, it is recommended
that the T7230A also generate the system frame synchronization signal.
Concentration Highway Master Mode (CHIMM).
A 0 enables the system’s frame synchronization signal
(FS) to drive both the receive and transmit paths of the T7230’s concentration highway interface.
A 1 enables the T7230’s transmit concentration interface to generate a system frame synchronization sig-
nal derived from the receive line interface. The T7230’s system frame synchronization signal is generated
on the OFS output pin (pin #50). Applications using the receive line clock as the reference clock signal of
the system are recommended to enable this mode and use the OFS signal generated by the T7230.
Superframe Select (SFSEL).
A 0 enables the signaling superframe pulse referenced from the CHI data.
The superframe signal will be active-high during time slot 0 of the CHI at the beginning of the superframe.
A 1 enables the signaling superframe pulse referenced from the frame sections. The superframe signal
will be active-high during bit 0 of time slot 0 of the framer data at the beginning of the superframe.
Framer Factory Test Modes (FFT0—FFT1).
These bits must always be 0.
In CEPT mode only:
1
4
5
6—7
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明:
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