參數(shù)資料
型號(hào)： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 26/110頁(yè)
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
22
Lucent Technologies Inc.
ISDN Primary Rate Interface
(continued)
The time slots assigned to the other channels (B, H0, or H11) are numbered 1 to 23 or 1 to 24, depending on the
presence of a D or E channel. The timing procedures, based on providing satisfactory customer service, imply that
the NT derives its timing from the network clock and the TE synchronizes its timing to a signal received from the
NT.
The electrical charcteristics of the 2.048 Mbits/s interface are also described in the ITU Recommendation G.703.
Framing characteristics are described in the ITU Recommendation G.704. The frame structure consists of 32 time
slots, numbered 0 to 31. Time slot 0 contains the frame alignment signal. Time slot 16 contains the D or E channel
when either is present. The remaining time slots (1—15 and 17—31) are available for the other channels (B, H0, or
H12). Timing procedures are the same as those for the 1.544 Mbits/s interface.
Line Interface
Physical Interface
The transmit line interface for the T7230A consists of the XPD, XND, XFD, XFCK, and XLCK pins. The receive line
interface consists of the RPD, RND, RFD, RFCK and RLCK pins. When programmed for single-rail mode, the trans-
mit framer drives XPD with valid data while XND is forced to ZERO. The receive framer accepts data on RPD as
valid non-return-to-zero single-rail data; RND = 1 on the rising edge of RLCK will cause the BPV counter to incre-
ment by one. Figure 6 shows the timing for the transmit and receive line interfaces.
5-4558(F).a
Figure 6. Transmit Framer XLCK to XND, XPD and Receive Framer RND, RPD to RLCK Timing
t1
t2r-f
t2f-r
t3
t4
t5
PLLCK
XLCK
XND, XPD
RLCK
RND, RPD
FRMRCLK
t7 = RPD, RND HOLD FROM RISING RLCK = 50 ns
t6
t7
t8
t1-DS1 = 648 ns (LOW FREQUENCY)/162 ns (HIGH FREQUENCY)
t1-CEPT = 488 ns (LOW FREQUENCY)/122 ns (HIGH FREQUENCY)
t2r-f: t2f-r: PLLCK TO XLCK DELAY = 80 ns
t3-DS1 = 648 ns
t3-CEPT = 488 ns
t4 = XLCK TO VALID XPD, XND = 50 ns
t5-CEPT = 488 ns
t5-DS1 = 648 ns
t6 = RPD, RND SETUP TO RISING RLCK = 100 ns
t8r-f: t8f-r: RLCK TO FRMRCLK DELAY = 100 ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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