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參數(shù)資料
| 型號： | T7230A |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 9/110頁 |
| 文件大?。?/td> | 752K |
| 代理商： | T7230A |
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Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
5
Lucent Technologies Inc.
List of Tables
Tables
Page
Table 1. Pin Descriptions for the 68-Pin Package ..................................................................................................13
Table 2. Pin Descriptions for the 80-Pin Package ..................................................................................................17
Table 3. Single-Rail Encoding ................................................................................................................................23
Table 4. AMI Encoding ...........................................................................................................................................23
Table 5. DS1 ZCS Encoding ..................................................................................................................................24
Table 6. DS1 B8ZS Encoding ................................................................................................................................24
Table 7. ITU HDB3 Coding and DCPAT Binary Coding .........................................................................................24
Table 8. T-Carrier Hierarchy ..................................................................................................................................25
Table 9. D4 Superframe Format ............................................................................................................................26
Table 10. DDS Channel 24 Format ........................................................................................................................26
Table 11.
SLC
-96 Data Link Block Format .............................................................................................................28
Table 12.
SLC
-96 Line Switch Message Codes .....................................................................................................28
Table 13. Extended Superframe (ESF) Structure ..................................................................................................29
Table 14. T1 Loss of Frame Alignment Criteria .....................................................................................................30
Table 15. T1 Frame Alignment Procedures ...........................................................................................................31
Table 16. Robbed-Bit Signaling Options ................................................................................................................32
Table 17.
SLC
-96 9-State Signaling Format ..........................................................................................................32
Table 18. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame ....................................................33
Table 19. ITU CRC-4 Multiframe Structure of the T7230A ....................................................................................36
Table 20. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure .......................................42
Table 21. CEPT IRSM Signaling Multiframe Structure ..........................................................................................43
Table 22. Associated Signaling Mode CHI 2-Byte Time-Slot Format ....................................................................50
Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels ...................................50
Table 24. Loss of Frame Alignment Alarm Conditions ...........................................................................................51
Table 25. Remote Frame Alarm Conditions ...........................................................................................................51
Table 26. Alarm Indication Signal Conditions ........................................................................................................52
Table 27. Sa6 Bit Coding Recognized by the T7230A Receive Framer ................................................................54
Table 28. Sa6 Bit Coding of NT1 Interface Events Recognized by the T7230A Receive Framer .........................54
Table 29. The T7230A Event Counters Definition ..................................................................................................56
Table 30. T7230A Automatic Enable Commands ..................................................................................................59
Table 31. T7230A On-Demand Commands ...........................................................................................................60
Table 32. Summary of the Concentration Highway Interface Parameter for the T7230A ......................................62
Table 33. Programming Values for XOFF[2:0] and ROFF[2:0] when CMS = 0 .....................................................63
Table 34. Programming Values for XOFF[2:0] when CMS = 1 ..............................................................................63
Table 35. Programming Values for ROFF[2:0] when CMS = 1 ..............................................................................63
Table 36. T7230A Status and Control Blocks Address Range ..............................................................................70
Table 37. Interrupt Status Register (SR0) ..............................................................................................................71
Table 38. Facility Alarm Condition (SR1) ...............................................................................................................72
Table 39. Remote End Alarm Condition (SR2) ......................................................................................................73
Table 40. Facility Errored Event (SR3) ..................................................................................................................74
Table 41. Facility Event Register 1 (SR4) ..............................................................................................................75
Table 42. Facility Event Register 2 (SR5) ..............................................................................................................76
Table 43. CRC Error Counter Register (SR6—SR7) .............................................................................................77
Table 44. Errored Event Counter Register (SR8—SR9) ........................................................................................77
Table 45. Errored Seconds Counter Register (SR10—SR11) ...............................................................................77
Table 46. Bursty Errored Seconds Counter Register (SR12—SR13) ....................................................................77
Table 47. Severely Errored Seconds Counter Register (SR14—SR15) ................................................................77
Table 48. Unavailable Seconds Counter Register (SR16—SR17) ........................................................................78
Table 49. Double Bipolar Violation Counter Register (SR18—SR19) ....................................................................78
Table 50. Framing Bit Error Counter Register (SR20) ...........................................................................................78
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相關代理商/技術參數(shù) |
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| T-7230A--ML | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| T7230-ML3 | 制造商:AGERE 功能描述: |
| T7-231A1 | 功能描述:撥動開關 ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明: |
| T7-231A2 | 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD, |
| T7-231A2D | 功能描述:撥動開關 ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明: |
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