參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 50/110頁
文件大小： 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
46
Lucent Technologies Inc.
CEPT Time Slot 0 FAS/NOT FAS Control Bits
(continued)
NOT FAS A-Bit Sources
The A bit, as described in ITU Rec. G.704 Section 2.3.2 Table 4a/G.704, is the remote alarm indication bit. In
undisturbed conditions, this bit is set to 0 and transmitted to the line. In the LFA state, receive A bit = 1 in the status
registers. The A bit is set to 1 and transmitted to the line for the following conditions:
1.
Setting the transmit A bit = 1 control bit.
2.
Optionally for the following alarm conditions:
A. The duration of loss of basic frame alignment as described in ITU Rec. G.706 Section 4.1.1
1
, or ITU Rec.
G.706 Section 4.3.2
2
, or due to on-demand reframe from control register (XALFA).
B. The duration loss of CRC-4 multiframe alignment (XALMFA).
C. The duration loss of CRC-4 multiframe alignment after either the 100 ms or 400 ms timer expires.
1. LFA is due to three consecutive frames with incorrect frame alignment signals having been received or three consecutive frames not contain-
ing the frame alignment signals with bit 2 received with an error.
2. LFA is due to detecting 915 out of 1000 received CRC-4 errored blocks.
NOT FAS Sa-Bit Sources
The Sa bits in the NOT FAS frame can be a 4 kbits/s data link to and from the remote end. The sources for the Sa
bits are by order of priority.
1.
The Sa control register (default source).
2.
The facility data link interface.
3.
The CHI system interface.
A. This is the default mode and requires the received system data (DRA or DRB) to maintain a biframe
alignment pattern where frames containing Sa bit information have bit 2 of time slot 0 in the binary 1 state
followed by frames not containing Sa bit information having bit 2 of time slot 0 in the binary 0 state. This
ensures the proper alignment of the Sa received system data to the transmit line Sa data. Whenever this
requirement is not met by the system, the T7230A transmit framer will enter a loss of biframe alignment
condition (indication is given in the status registers) and then search for the pattern; in the loss of biframe
alignment state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si
data). When the transmit framer locates a new biframe alignment pattern, an indication is given in the
status registers and the transmit framer resumes normal operations.
B. When PR3, bit 1 = 1 and PR6, bit 6 = 1, the transmit framer will align its NOT FAS time slot to either the
odd-numbered framers from the receive CHI interface and transmit the Sa bit positions in this frame as
valid Sa data. The choice of even or odd is arbitrary. The “other” frame is ignored.
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相關代理商/技術參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關 ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關 ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
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