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參數(shù)資料
| 型號(hào)： | T7230A |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 41/110頁 |
| 文件大?。?/td> | 752K |
| 代理商： | T7230A |
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Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
37
Lucent Technologies Inc.
Frame Formats
(continued)
CEPT Time Slot 0 CRC-4 Multiframe Structure
(continued)
Representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0,
bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is
frame 7 or frame 15, bit 256. Similarly, C
1
is defined to be the most significant bit of the remainder and C
4
the least
significant bit of the remainder. The encoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.2, fol-
lows:
1.
The CRC-4 bits in the SMF are replaced by binary 0s.
2.
The SMF is then acted upon the multiplication/division process referred to above.
3.
The remainder resulting from the multiplication/division process is stored, ready for insertion into the respec-
tive CRC-4 locations of the next SMF.
The decoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.3, follows:
1.
A received SMF is acted upon by the multiplication/division process referred to above, after having its CRC-4
bits extracted and replaced by 0s.
2.
The remainder resulting from this division process is then stored and subsequently compared on a bit-by-bit
basis with the CRC bits received in the next SMF.
3.
If the remainder calculated in the decoder exactly corresponds to the CRC-4 bits received in the next SMF, it is
assumed that the checked SMF is error-free.
CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA)
Loss of basic frame alignment forces the receive framer into a loss of CRC-4 multiframe alignment state. This state
is reported by way of the status registers, and once basic frame alignment is achieved, a new search for CRC-4
multiframe alignment is initiated. During a loss of CRC-4 multiframe alignment state:
1.
The CRC-4 error counter is halted.
2.
The CRC-4 error monitoring circuit for errored seconds and severely errored seconds is halted.
3.
The received E-bit monitoring circuit is halted.
4.
Receive continuous E-bit monitoring is halted.
5.
All receive Sa6 code monitoring and counting functions are halted.
6.
Optionally, A = 1 may be automatically transmitted to the line.
7.
Optionally, E = 0 may be automatically transmitted to the line.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T-7230A--ML | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| T7230-ML3 | 制造商:AGERE 功能描述: |
| T7-231A1 | 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明: |
| T7-231A2 | 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD, |
| T7-231A2D | 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明: |
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