參數(shù)資料
型號(hào)： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 54/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
50
Lucent Technologies Inc.
Signaling Access
(continued)
Associated Signaling Mode
Signaling information in the associated signaling mode (ASM) is allocated an 8-bit system time slot in conjunction
with the data information for a particular channel. The system data rate in the ASM mode is 4.096 Mbits/s. Each
system channel consists of an 8-bit payload time slot followed by its associated 8-bit signaling time slot. The format
of the signaling byte is identical to the signaling registers. In the default ASM mode, writing the transmit signaling
registers will corrupt the transmit signaling data. In the TSR-ASM mode, the system must write into the F and G
bits
1
of the transmit signaling registers to program the robbed-bit signaling state mode of each DS0.
In the TSR-ASM mode, the system writes into the F and G bits
1
of the transmit signaling registers to program the
robbed-bit signaling state mode of each transmit and received DS0. This mode is enabled by programming PR10,
bit 5 to 1 in any DS1 mode. The F and G bits in the system data are ignored.
The received signaling data can be obtained from both the system interface and the receive signaling registers.
The associated signaling mode is valid for both the T1 and CEPT framing formats. Table 22 illustrates the ASM
time slot format for valid channels.
* In the CEPT IRSM format, this bit position contains the per-channel E0-31 control information. In all other formats this bit is ignored.
In the DS1-TSR-ASM mode and CEPT frame formats, these bits are ignored.
The P bit is the parity-sense bit calculated over the 8 data bits, the ABCD (and E bits), and the P bit. The identical sense of the received sys-
tem P bit in the transmitted signaling data is echoed back to the system in the received signalling information.
The T1 framing formats require rate adaption from the line-interface 1.544 Mbits/s bit stream to the system-inter-
face 4.096 Mbit/s bit stream. The rate adaption results in the need for stuffed time slots on the system interface.
Table 23 illustrates the ASM format for T1 stuffed channels used by the T7230A. The stuffed data byte contains the
programmable idle code (default = FE
hex
), while the signaling byte is ignored.
1. All other bits in the signaling registers are ignored, while the F and G bits in the received DR stream are ignored.
Table 22. Associated Signaling Mode CHI 2-Byte Time-Slot Format
ASM CHI Time Slot
PAYLOAD DATA
3
4
SIGNALING INFORMATION
A
B
C
D
1
2
5
6
7
8
E
*
F
G
P
Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels
ASM CHI Time Slot
PAYLOAD DATA
1
1
SIGNALING INFORMATION
X
X
X
X
1
1
1
1
1
0
X
X
X
X
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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