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參數(shù)資料
| 型號： | T7230A |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 74/110頁 |
| 文件大?。?/td> | 752K |
| 代理商： | T7230A |
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Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
70
Lucent Technologies Inc.
Register Structure
T7230A registers are structured into six groups:
1.
2.
3.
4.
5.
6.
Clear-on-read interrupt generating status registers (SR0—SR5).
Cleared-on-read count registers (SR6—SR20).
CEPT spare bit registers (SR21—SR22).
Parameter registers (PR0—PR31).
Receive signaling registers (RSR0—RSR31).
Transmit signaling registers (TSR0—TSR31).
Each block of registers is grouped as shown in Table 36.
Table 36. T7230A Status and Control Blocks Address Range
All status registers are clocked with the framer unit receive line clock.
Status registers SR0, SR3, SR4, and SR5 and all counting registers are cleared on read (COR).
When reading the clear-on-read status registers, only those bits in the 1 state at the time of the read are cleared.
Status registers SR1 and SR2 generate interrupts at the onset of the condition. The condition monitored in these
bits are latched and are cleared on read if the condition no longer exists. If the condition is still present at the time
of the read, then the bit is cleared by the T7230A when the given condition is no longer observed by the T7230A.
On all 16-bit counter registers both bytes are cleared only after reading both bytes, regardless of the order in which
they are read. Once a read is initiated on one of the bytes, the updating of that counter is disabled and remains dis-
abled until both bytes are read. All events during this interval are lost.
The count registers stop at the all ones state. This state may be programmed to generate an interrupt when it is
reached.
T7230A Register Block
Decimal Address Range
0—5
6—20
21—22
23—31
32—63
64—95
96—127
Interrupt Status Registers (COR)
Status Counters (COR)
Received CEPT Time Slot 0 and Time Slot 16 Control Bits
Reserved
Receive Signaling Registers
Parameter (Configuration) Registers
Transmit Signaling Registers
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參數(shù)描述 |
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| T-7230A--ML | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| T7-231A1 | 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明: |
| T7-231A2 | 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD, |
| T7-231A2D | 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明: |
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