參數(shù)資料
型號(hào)： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 11/110頁(yè)
文件大小： 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
7
Lucent Technologies Inc.
List of Figures
Figures
Page
Figure 1. Basic T7230A System Interface Configuration .........................................................................................9
Figure 2. Functional Block Diagram of the T1/E1 Primary Access Framer/Controller (PAC) ................................10
Figure 3. The T7230A’s 68-Pin Plastic Leaded Chip Carrier (PLCC) Package Option Pin Assignments ..............11
Figure 4. The T7230A’s 80-Pin Thin Quad Flat Package (TQFP) Package Option Pin Assignments ...................12
Figure 5. ISDN Primary Rate Interface Reference Points ......................................................................................21
Figure 6. Transmit Framer XLCK to XND, XPD and Receive Framer RND, RPD to RLCK Timing .......................22
Figure 7. T7230A Facility Data Link Timing ...........................................................................................................23
Figure 8. T1 Frame Structure .................................................................................................................................25
Figure 9. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe
Structures ................................................................................................................................................35
Figure 10. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer ..................................39
Figure 11. T7230A Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4
Equipment Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991) ....................41
Figure 12. CEPT AFS and NOT FAS System Interface Format ............................................................................47
Figure 13. The T and V Reference Points for a Typical CEPT E1 Application ......................................................55
Figure 14. T7230A’s Loopback and Test Transmission Modes .............................................................................57
Figure 15. 15-Stage Shift Register Used to Generate the Pseudorandom Signal .................................................58
Figure 16. CHI DX and DR to CLKXR Relationship with CMS = 0 (CEX = 3 and CER = 4, Respectively) ...........64
Figure 17. CHI DX and DR to CLKXR Relationship with CMS = 1 (CEX = 3 and CER = 6, Respectively) ...........64
Figure 18. T7230A Phase Detector Circuitry .........................................................................................................66
Figure 19.
Intel
Interface Mode Read (A) and Write (B) Cycle Timing ...................................................................68
Figure 20.
Motorola
Interface Mode Read (A) and Write (B) Cycle Timing ............................................................69
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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