參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 24/110頁
文件大小： 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
20
Lucent Technologies Inc.
Pin Information
(continued)
Table 2. Pin Descriptions for the 80-Pin Package
(continued)
1. I
u
indicates an internal pull-up.
Pin
65
Symbol
FRBIT
Type
1
O
Name and Function
Receive Framing Bit.
In DS1 framing formats, this pin outputs the value
of the framing bit associated with the current CHI frame. The value is valid
for the duration of the CHI frame. In CEPT mode, this pin is forced to a
1 state.
Transmit Facility Data Link Clock.
In DS1-DDS with data link access,
this is an 8 kHz clock signal. Otherwise, this is a 4 kHz clock signal.
Transmit Facility Data Link.
Serial input facility data link bit stream for
insertion into the transmit line data stream by the transmit framer. In DS1-
DDS with data link access, this is an 8 kbits/s signal. Otherwise, this is a
4 kbits/s signal.
Receive Facility Data Link Clock.
In DS1-DDS with data link access, this
is an 8 kHz clock signal. Otherwise, this is a 4 kHz clock signal.
Receive Facility Data Link.
Serial output facility data link bit stream
extracted from the receive line data stream by the receive framer. In DS1-
DDS with data link access, this is an 8 kbits/s signal. Otherwise, this is a
4 kbits/s signal. During a loss of frame alignment, the receive framer will
force this pin to a 1 state.
Loss of Transmit Clock.
The T7230A drives this pin high when it detects
PLLCK stuck in a 0 state or a 1 state for an interval greater than 250
μ
s.
Loss of Receive Clock.
The T7230A drives this pin high when it detects
RLCK stuck in a 0 state or a 1 state for an interval greater than 250
μ
s.
Receive Negative-Rail Data.
Dual-rail, non-return-to-zero serial data
latched by the rising edge of RLCK. Data rates: DS1—1.544 Mbits/s;
CEPT—2.048 Mbits/s.
In single-rail mode, if RND = 1 at the rising edge of RLCK, the BPV
counter increments by one.
Receive Positive-Rail Data.
Dual-rail, non-return-to-zero serial data
latched by the rising edge of RLCK. Data rates: DS1—1.544 Mbits/s;
CEPT—2.048 Mbits/s.
In single-rail mode, RPD is receive data.
Receive Line Interface Clock.
1.544 MHz DS1 or 2.048 MHz input signal
used by the receive framer.
Transmit Negative-Rail Data.
Dual-rail, non-return-to-zero serial data
latched out by the rising edge of XLCK. Data rates: DS1—1.544 Mbits/s;
CEPT—2.048 Mbits/s.
Transmit Positive-Rail Data.
Dual-rail, non-return-to-zero serial data
latched out by the rising edge of XLCK. Data rates: DS1—1.544 Mbits/s;
CEPT—2.048 Mbits/s.
No Connect.
Transmit Line Interface Clock.
1.544 MHz DS1 or 2.048 MHz input sig-
nal used by the transmit framer.
Ground.
No Connect.
66
XFCK
O
67
XFD
I
68
RFCK
O
69
RFD
O
70
LOPLLCK
O
71
LORLCK
O
72
RND
I
73
RPD
I
74
RLCK
I
75
XND
O
76
XPD
O
77
78
NC
XLCK
—
O
79
80
V
SS
NC
—
—
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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