
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
3
Lucent Technologies Inc.
Table of Contents
(continued)
Contents
Page
Concentration Highway Interface (CHI) .................................................................................................................61
CHI Parameters .................................................................................................................................................62
CHI Offset Programming ...................................................................................................................................63
Phase-Lock Loop Circuit ........................................................................................................................................65
Microprocessor Interface ........................................................................................................................................67
Register Structure ..................................................................................................................................................70
Status/Counter Registers ..................................................................................................................................71
Interrupt Status Register (SR0) ....................................................................................................................71
Facility Alarm Condition Register (SR1) .......................................................................................................72
Remote End Alarm Register (SR2) ..............................................................................................................73
Facility Errored Event Register (SR3) ..........................................................................................................74
Facility Event Register 1 (SR4) ....................................................................................................................75
Facility Event Register 2 (SR5) ....................................................................................................................76
CRC-4 Error Counter Register (SR6—SR7) ................................................................................................77
Errored Event Counter Register (SR8—SR9) — 16-Bit Counter .................................................................77
Errored Seconds Counter Register (SR10—SR11) .....................................................................................77
Bursty Errored Seconds Counter Register (SR12—SR13) ..........................................................................77
Severely Errored Seconds Counter Register (SR14—SR15) — 16-Bit Counter .........................................77
Unavailable Seconds Counter Register (SR16—SR17) — 16-Bit Counter .................................................78
Bipolar Violation Counter Register (SR18—SR19) ......................................................................................78
Frame Bit Error Counter Register (SR20) ....................................................................................................78
Received Sa Register (SR21) ......................................................................................................................78
Received Si and X Register (SR22) .............................................................................................................78
Received Signaling Registers: DS1 Format .................................................................................................79
Receive Signaling Registers: CEPT Format ................................................................................................79
Parameter/Control Registers .............................................................................................................................80
Primary Interrupt Group Enable Register (PR0) ..........................................................................................80
Framer Mode Option Register (PR1) ...........................................................................................................81
Automatic Transmission Enable Register (PR2) ..........................................................................................82
On-Demand Transmit Register 1 (PR3) .......................................................................................................82
On-Demand Transmit Register 2 (PR4) .......................................................................................................83
Framer Squelch Code Register (PR5) .........................................................................................................84
Transmit Sa Source Register (PR6) .............................................................................................................84
Si-Bit/X-Bit/E-Bit Source Register (PR7) ......................................................................................................85
Framer Exercise Register (PR8) ..................................................................................................................85
System Interface Control Register (PR9) .....................................................................................................88
Signaling Mode Register (PR10) ..................................................................................................................89
System Clock Control Register (PR11) ........................................................................................................90
Framer Idle Code Register (PR12) ..............................................................................................................91
CHI Common Control Register (PR13) ........................................................................................................91
CHI Transmit Control Register (PR14) .........................................................................................................91
CHI Receive Control Register (PR15) ..........................................................................................................92
CHI Transmit Time-Slot Enable Registers (PR16—PR19) ..........................................................................92
Receive Time-Slot Enable Registers (PR20—PR23) ..................................................................................92
CHI Transmit Highway Select Registers (PR24—PR27) .............................................................................93
CHI Receive Highway Select Registers (PR28—PR31) ..............................................................................93
Transmit Signaling Registers: DS1 Format ..................................................................................................93
Transmit Signaling Registers: CEPT Format ...............................................................................................94