參數(shù)資料
型號(hào)： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 94/110頁(yè)
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
90
Lucent Technologies Inc.
Register Structure
(continued)
Parameter/Control Registers
(continued)
System Clock Control Register (PR11)
Table 67. System Clock Control Register (PR11)
Transmit Signal
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X
X
X
X
High-Frequency_Low-Frequency PLLCK Clock Mode (HFLF = 0).
Enables the low-frequency PLLCK mode for the divide-down circuit in
the internal phase-lock loop section (DS1 PLLCK = 1.544 MHz; CEPT
PLLCK = 2.048 MHz). The divide-down circuit will produce an 8 kHz
signal on DPLLCK.
High-Frequency_Low-Frequency PLLCK Clock Mode (HFLF = 1).
A 1 enables the high-frequency PLLCK mode for the divide-down circuit
in the internal phase-lock-loop section (DS1: PLLCK =
6.176 (4 x 1.544) MHz; CEPT: 8.192 (4 x 2.048) MHz). The divide-
down circuit will produce a 32 kHz signal on DPLLCK.
Concentration Highway Clock Mode (CMS = 0).
CLKXR frequency and CHI data (DRA, DRB, DXA, and DXB) rates are
equal.
Concentration Highway Clock Mode (CMS = 1).
CLKXR frequency is 2X the CHI data (DRA, DRB, DXA, and DXB) rate.
Concentration Highway Data Rate Select (CDRS = 0).
CHI data (DRA, DRB, DXA, and DXB) rate is 2.048 Mbits/s.
Concentration Highway Data Rate Select (CDRS = 1).
CHI data (DRA, DRB, DXA, and DXB) rate is 4.096 Mbits/s.
Software Reset (SWRST = 0).
T7230A operates as programmed.
Software Reset (SWRST = 1).
T7230A is placed into reset state where all parameter registers (exclud-
ing this bit) are forced into the default state. SWRST must be set to the
0 state to deassert this state.
Software Restart (SWRSTRT = 0).
T7230A operates as programmed.
Software Restart (SWRSTRT = 1).
T7230’s internal counters are placed into reset state. The state of the
parameter registers remain as programmed. SWRSTRT must be set to
the 0 state to deassert this state.
Open Collector Enable (OCE = 0).
CHI outputs DXA and DXB generate a positive pulse (5 V) to represent
a binary 1.
Open Collector Enable (OCE = 1).
CHI outputs DXA and DXB are placed in a high-impedance state to
represent a binary 1.
Full System Loopback (FSLB = 0).
T7230A transmits and receives data as programmed.
Full System Loopback (FSLB = 1).
T7230A loops back to the system DRA and/or DRB data to DXA and/or
DXB. Data transverses the entire transmit path and receive path of the
T7230.
Framer Factory Test (FFT3).
This bit must always be 0.
X
X
X
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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