參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 66/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
62
Lucent Technologies Inc.
Concentration Highway Interface (CHI)
(continued)
CHI Parameters
The eight parameters that define the receive and transmit CHI timing relative to the frame strobe (FS) are given in
Table 32.
Table 32. Summary of the Concentration Highway Interface Parameters for the T7230A
Name
Description
FE
Frame Edge
. FE = 0 (1); FS is sampled on the falling (rising) edge of CLKXR. FE is
used in both the receive and transmit directions. In CHIMM (CHI master mode), pin
50 (OFS) outputs a transmit frame strobe to provide synchronization for the DXA and
DXB. When FE = 1 (or 0), OFS is centered around rising (or falling) edge of CLKXR.
In this mode, FS is used for receive data on CHI and OFS is used for transmit data on
CHI. (OFS must be physically connected to FS if OFS is the source of the frame sync
signal for the DRA, DRB interface.) The timing for OFS in CHIMM = 1 mode is
identical to the timing for FS in CHIMM = 0 mode.
Clock Select Mode (CMS)
Clock Select Mode
. When CMS = 0, the concentration highway clock (CLKXR) and
data (DRA, DRB, DXA, or DXB) have the same rate. When CMS = 1, the
concentration highway clock (CLKXR) is twice the rate of CHI data.
XCE
Transmitter Clock Edge
. XCE = 0 (1), DX is clocked on the falling (rising) edge of
CLKXR.
RCE
Receiver Clock Edge
. RCE = 0 (1), DR is latched on the falling (rising) edge of
CLKXR.
XOFF2—XOFF0
Transmitter Bit Offset
. Three-bit binary offset, relative to FS, for the first bit of the
transmit time slot. For CMS = 1, the offset is twice the number of CLKXR clock periods
by which transmission of the first bit is delayed. For CMS = 0, the offset is the number
of CLKXR cycles by which the first bit is delayed.
ROFF2—ROFF0
Receiver Bit Offset
. Three-bit binary offset, relative to the FS, for the first bit of the
receive time slot. For CMS = 1, the offset is twice the number of CLKXR clock periods
by which the first bit is delayed. For CMS = 0, the offset is the number of CLKXR
cycles by which the first bit is delayed.
XBYOFF5—XBYOFF0
Transmitter Byte Offset
. Six-bit binary byte-offset from the framing strobe (FS) to the
beginning of the next frame on the transmit highway. Note that in the ASM mode, a
frame consists of 64 bytes; whereas in other modes, a frame contains 32 bytes. In the
2.048 Mbits/s mode, the allowable offsets are 0—31 bytes. In both the
4.096 Mbits/s modes, the allowable offsets are 0—63 bytes.
RBYOFF5—RBYOFF0
Receiver Byte Offset
. Six-bit binary byte-offset from FS to the beginning of the
receive CHI frame. Note that in the ASM mode, a frame consists of 64 bytes; whereas
in other modes, a frame contains 32 bytes. In the 2.048 Mbits/s mode, the allowable
offsets are 0—31 bytes. In both the 4.096 Mbits/s modes, the allowable offsets are
0—63 bytes.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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