參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 6/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
Features .................................................................................................................................................................. 1
Functional Description ............................................................................................................................................. 8
Pin Information ....................................................................................................................................................... 11
ISDN Primary Rate Interface ................................................................................................................................. 21
Line Interface ......................................................................................................................................................... 22
Physical Interface ............................................................................................................................................. 22
Line Encoding ................................................................................................................................................... 23
Single Rail ................................................................................................................................................... 23
Alternate Mark Inversion (AMI) .................................................................................................................... 23
DS1 Zero Code Suppression (ZCS) ................................................................................................................. 24
T1 Binary 8 Zero Code Suppression ........................................................................................................... 24
High-Density Bipolar of Order 3 (HDB3) ........................................................................................................... 24
Frame Formats ...................................................................................................................................................... 25
T1 Framing Structures ...................................................................................................................................... 25
Frame, Superframe, and Extended Superframe Definitions ....................................................................... 25
D4 Frame Format ........................................................................................................................................ 26
Digital Data Service (DDS) Frame Format .................................................................................................. 26
SLC
-96 Frame Format ................................................................................................................................ 27
Extended Superframe ................................................................................................................................. 29
T1 Loss of Frame Alignment (LFA) ................................................................................................................... 30
T1 Frame Recovery Alignment Algorithms ....................................................................................................... 31
T1 Robbed-Bit Signaling ................................................................................................................................... 32
SLC
-96 9-State Signaling ............................................................................................................................ 32
CEPT 2.048 Basic Frame Structure ................................................................................................................. 33
CEPT Loss of Basic Frame Alignment (LFA) ................................................................................................... 33
CEPT Loss of Frame Alignment Recovery Algorithm ....................................................................................... 34
CEPT Time Slot 0 CRC-4 Multiframe Structure ................................................................................................ 36
CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA) ................................................................................. 37
CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms ................................................................... 38
CRC-4 Multiframe Alignment Algorithm with 8 ms Timer ............................................................................ 38
CRC-4 Multiframe Alignment Algorithm with 100 ms Timer ........................................................................ 38
CRC-4 Multiframe Alignment Search Algorithm with 400 ms Timer ............................................................ 40
CEPT Time Slot 16 Multiframe Structure .......................................................................................................... 42
Channel Associated Signaling ..................................................................................................................... 42
IRSM Signaling ............................................................................................................................................ 43
CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA) ...................................................................... 44
CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm ........................................................... 44
CEPT Time Slot 0 FAS/NOT FAS Control Bits ...................................................................................................... 45
FAS/NOT FAS Si- and E-Bit Source ................................................................................................................. 45
NOT FAS A-Bit Sources ................................................................................................................................... 46
NOT FAS Sa-Bit Sources ................................................................................................................................. 46
Sa Facility Data Link Access ............................................................................................................................ 48
Microprocessor Sourcing of the Si and Sa4 to Sa8 Bits ................................................................................... 48
CEPT Time Slot 16 X0—X2 Control Bits ............................................................................................................... 48
Signaling Access ................................................................................................................................................... 49
Transparent Signaling (TSIG = 1) ..................................................................................................................... 49
Microprocessor Control Registers .................................................................................................................... 49
Associated Signaling Mode .............................................................................................................................. 50
Alarms and Performance Monitoring ..................................................................................................................... 51
Loopback and Transmission Modes ................................................................................................................. 57
Transmit Line Test Patterns .............................................................................................................................. 58
Automatic and On-Demand Commands ........................................................................................................... 59
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相關代理商/技術參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關 ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關 ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
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