
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
24
Lucent Technologies Inc.
Line Interface
(continued)
DS1 Zero Code Suppression (ZCS)
Zero code suppression is a technique known as pulse stuffing in which the least significant bit (LSB) of each time
slot is forced to a logic 1 state (or stuffed with a one). The scheme, shown in Table 5, limits the data rate of each
time slot from 64 kbits/s to 56 kbits/s.
The T7230A default ZCS format stuffs the seventh bit of those time slots programmed for robbed-bit signaling (as
defined in the signaling control registers with the F and G bits) that contain all zeros.
In the framer mode or when TSIG = 1, ZCS is applied to all transmit time slots.
Table 5. DS1 ZCS Encoding
T1 Binary 8 Zero Code Suppression
The T7230A default line code is B8ZS. Clear channel transmission can be accomplished using binary 8 zero code
suppression (B8ZS). Eight consecutive 0s are replaced with the B8ZS code. This code consists of two bipolar vio-
lations in bit position 4 and 7 and valid bipolar marks in bit positions 5 and 8. The receiving end recognizes this
code and replaces it with the original string of eight 0s. Table 6 shows the encoding of a string of 0s using B8ZS.
B8ZS can be used in any DS1 frame.
High-Density Bipolar of Order 3 (HDB3)
The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3).
HDB3 uses a substitution code that acts on strings of four 0s. The substitute HDB3 codes are 000V and B00V,
where V represents a violation of the bipolar rule and B represents an inserted pulse conforming to the AMI rule
defined in ITU Rec. G.701, item 9004. The choice of the B00V or 000V is made such that the number of B pulses
between consecutive V pulses is odd. In other words, successive V pulses are of alternate polarity so that no direct
current (dc) component is introduced. The substitute codes follow each other if the string of 0s continues. The
choice of the first substitute code is arbitrary. A line code error is as a bipolar violation and consists of two pulses of
the same polarity that are not defined as one of the two substitute codes. An example is shown in Table 7.
Table 7. ITU HDB3 Coding and DCPAT Binary Coding
Input Bit Stream
AMI Data
(framer mode)
T7230A Default AMI
00000000
00000010
01010000
01010010
00000000
00000010
00000000
00000010
00000010
01010000
00000000
(data time slot)
00000010
Table 6. DS1 B8ZS Encoding
Bit Positions
Before B8ZS
After B8ZS
1
0
0
2
0
0
3
0
0
4
0
V
5
0
B
6
0
0
7
0
V
8
0
B
—
1
B
—
0
0
—
1
B
1
0
0
2
0
0
3
0
0
4
0
V
5
0
B
6
0
0
7
0
V
8
0
B
Input Bit Stream
HDB3-Coded Data
HDB3-Coded Levels
HDB3 with 5 BPVs
1011
1011
–0+–
–0+–
0000
000V
000–
–000
1-BPV
01
01
0+
0+
0000
000V
000+
+00+
3-BPV
0000
B00V
–00–
0–––
5-BPV
0000
B00V
+00+
+00+
0000
B00V
–00–
–00–