參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 19/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
15
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions for the 68-Pin Package
(continued)
1. I
u
indicates an internal pull-up.
Pin
32
Symbol
RD_R/W
Type
1
I
Name and Function
Read_Read/Write.
While RD is low in the Intel interface mode, the T7230A
drives the data bus with the contents of the addressed register.
In the Motorola interface mode, this signal is asserted high for read
accesses or asserted low for write accesses.
Write_Data Strobe (Active-Low).
In the Intel mode, the value present on
the data bus is latched into the addressed register on the positive edge of
the signal applied to WR. In the Motorola mode, when AS = 0 and R/W = 0
(write), the value present on the data bus is latched into internal flip-flops on
the positive edge of the signal applied to DS; when AS = 0 and R/W = 1
(read), the T7230A drives the data bus with the contents of the addressed
register while DS = 0.
Microprocessor Data Bus.
Bidirectional data bus used for read and write
accesses. While the T7230A is not driving the data bus, the T7230A will
force these pin into an high-impedance state.
Ground.
Microprocessor Clock.
16 MHz microprocessor clock. Used only for timing
the internal RDY signal.
Microprocessor Address Bus.
Address bus used to access internal regis-
ters.
5 V Supply.
CHI Time-Slot Control for Port B.
The T7230A drives this pin low to enable
external bus drivers for active CHI time slots.
TID.
In the framer mode (FRMMOD = 0), this is the input data signal for the
transmit framer.
Receive CHI Data Port B.
Serial input system data at 2.048 Mbits/s or
4.096 Mbits/s.
Buffer Overflow.
In framer mode (FRMMOD = 0), this may be used in per-
formance monitoring to indicate an overflow event from an external elastic
store.
Transmit CHI Data Port B.
Serial output system data at 2.048 Mbits/s or
4.096 Mbits/s. This port is forced into a high-impedance state for all inactive
time slots.
Receive Signaling Inhibit.
In framer mode (FRMMOD = 0), this pin is
forced to a 1-state for the duration of a loss of frame, loss of superframe
(DS1), or loss of time slot 16 multiframe (CEPT) alignment state.
Framer Receive Line Clock.
Framer receive line clock used in the receive
framer section, derived from RLCK (same phase).
CHI Time-Slot Control for Port A (Active-Low).
The T7230A drives this pin
low to enable external bus drivers for active CHI time slots.
33
WR_DS
I
34—41
D7—D0
I/O
42
43
V
SS
MPCK
—
I
44—50
A6—A0
I
51
52
V
DD
—
I/O
TSCB_TID
53
DRB_BOF_CLKX
I
54
DXB_RSI
O
55
FRMRCLK
O
56
TSCA
O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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