參數(shù)資料
型號(hào): T7230A
廠商: Lineage Power
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 67/110頁
文件大小: 752K
代理商: T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
63
Lucent Technologies Inc.
Concentration Highway Interface (CHI)
(continued)
CHI Offset Programming
To facilitate bit offset programming, two additional parameters are introduced: CEX is defined as the clock edge
with which bit 7 of time slot 1 is transmitted; CER is defined as the clock edge on which bit 0 of time slot 0 is
latched. CEX and CER are counted relative to the edge on which the FS signal is sampled. Values of CEX and
CER depend upon the values of the eight parameters described above.
The following three tables give values of CEX and CER for various values of CMS, FE, XCE, and RCE, XOFF[2:0],
and ROFF[2:0]. The byte (time slot) offsets are assumed to be zero in the following examples.
Table 33. Programming Values for XOFF[2:0] and ROFF[2:0] when CMS = 0
Table 34. Programming Values for XOFF[2:0] when CMS = 1
Table 35. Programming Values for ROFF[2:0] when CMS = 1
FE
RCE/
XCE
ROFF[2:0] or XOFF[2:0]
011
100
10
12
9
11
9
11
10
12
000
4
3
3
4
001
6
5
5
6
010
8
6
6
8
101
14
13
13
14
110
16
15
15
16
111
18
17
17
18
CER
or
CEX
0
0
1
1
0
1
0
1
FE
XCE
XOFF[2:0]
000
4
3
3
4
001
8
7
7
8
010
12
11
11
12
011
16
15
15
16
100
20
19
19
20
101
24
23
23
24
110
28
27
27
28
111
32
31
31
32
0
0
1
1
0
1
0
1
CEX
FE
RCE
ROFF[2:0]
000
6
7
7
6
001
10
11
11
10
010
14
15
15
14
011
18
19
19
18
100
22
23
23
22
101
26
27
27
26
110
30
31
31
30
111
34
35
35
34
0
0
1
1
0
1
0
1
CER
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T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
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