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參數(shù)資料
| 型號(hào)： | T7230A |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 89/110頁(yè) |
| 文件大?。?/td> | 752K |
| 代理商： | T7230A |
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Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
85
Lucent Technologies Inc.
Register Structure
(continued)
Parameter/Control Registers
(continued)
Si-Bit/X-Bit/E-Bit Source Register (PR7)
These bits define the source of the E, X, and Si bits transmitted to the line.
Table 62. Si-Bit/X-Bit/E-Bit Source Register (PR7)
Framer Exercise Register (PR8)
Table 63. Framer Exercise Register (PR8)
Bits
0—2
Description
Transmit Time Slot 16 X0—X2 Bits (XTS16X0—XTS16X2).
The content of these bits are written into
CEPT signaling multiframe time slot 0 X bits.
X-Bit Source (XS).
A 1 enables the XTS16X[2:0] bits to be written into CEPT time slot 16 multiframe
frame 0. A 0 transmits the X bits transparently.
Transmit Bit 1 in FAS (XSiF).
The content of this bit can be transmitted to the line in bit 1 of the FAS. In
CRC-4 mode, this bit is used for E-bit data in frame 13, only valid if ATECE = 0.
Transmit Bit 1 in NOT FAS (XSiNF).
The content of this bit can be transmitted to the line in bit 1 of the
NOT FAS. In CRC-4 mode, this bit is used for E-bit data in frame 15, only valid if ATECE = 0.
Si-Bit Source (SIS).
A 0 forces XSiF and XSiNF to the line in FAS and NOT FAS, respectively. A 1, in
non-CRC-4 mode, transmits system data to the line transparently.
Automatic Transmit E Bit = 0 for Received CRC-4 Errored Events (ATECE).
A 1 transmits E = 0 to the
line whenever the receive framer detects a received CRC-4 errored checksum.
3
4
5
6
7
Bits
Description
FEX0—FEX5
FEX6
0
0
1
1
Framer Exercise Bits 0—5 (FEX0—FEX5). See Table 66.
Second Pulse Interval.
1 Second Pulse.
500 ms Pulse.
100 ms Pulse.
Manufacturer’s Test.
FEX7
0
1
0
1
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