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參數(shù)資料
| 型號(hào)： | T7230A |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 53/110頁 |
| 文件大小： | 752K |
| 代理商： | T7230A |
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Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
49
Lucent Technologies Inc.
Signaling Access
Signaling information can be accessed by three different methods: transparently through the CHI, through the
control registers, or through the CHI associated signaling mode.
Transparent Signaling (TSIG = 1)
Data at the received DRA and DRB interface passes through the T7230A undisturbed. The system is responsible
for placing (inserting) the signaling information in the appropriate time slot and frames. The T7230A generates a
signaling multiframe in the transmit and receive direction to facilitate the access of signaling information at the sys-
tem interface.
Microprocessor Control Registers
The information written into the F and G bits of the transmit signaling control registers define the robbed-bit signal-
ing mode for each channel for both the transmit and receive directions (TSIG = 0) in the T1 framing formats. The
per-channel programming allows the system to mix voice channels with data channels within the same frame. Note
that a receive-channel robbed-bit signaling mode is defined by the state of the F and G bits in the transmit signaling
control registers for that channel.
The microprocessor transmit signaling registers may be used in the associated signaling mode. In this mode (TSR-
ASM mode), the system writes into the F and G bits
1
of the transmit signaling registers to program the robbed-bit
signaling state mode of each transmit and received DS0. This mode is enabled by programming PR10, bit 5 to 1 in
any DS1 mode.
In the common channel signaling mode, data written in the transmit signaling registers is transmitted in channel 24
of the transmit line bit stream. The F and G bits are ignored in this mode. The received signaling data from channel
24 in T1 format or channel 16 in CEPT format, is stored in the receive signaling registers (RS0—RS23 for T1;
RS0—RS16 for CEPT).
1. All other bits in the signaling registers are ignored, while the F and G bits in the received DR stream are ignored.
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| T-7230A--ML | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| T7230-ML3 | 制造商:AGERE 功能描述: |
| T7-231A1 | 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明: |
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| T7-231A2D | 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明: |
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