參數資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數： 18/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
14
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions for the 68-Pin Package
(continued)
1. I
u
indicates an internal pull-up.
Pin
20
Symbol
CER
Type
1
O
Name and Function
Receive CRC Error.
Indication of a receive checksum error. In ESF, this pin
is asserted at the onset of the CRC-6 error and remains asserted for the
duration of the extended superframe. In CEPT, this pin is asserted once for
the errored checksum block for a 1-byte interval.
Error Phase-Lock Loop Signal.
The error signal proportional to the phase
difference between DCLKXR and DPLLCK as detected from the internal
PLL circuitry.
Divided-Down Phase-Lock Loop Clock.
32 kHz or 8 kHz clock signal
derived from the PLLCK input signal.
Divided-Down CHI Clock.
32 kHz or 8 kHz clock signal derived from the
CLKXR input signal.
Phase-Lock Loop Clock.
This clock signal is used to clock the transmit
framer. This signal should be phase-locked to the CLKXR clock signal.
DS1—1.544 MHz for low-frequency PLL mode.
DS1—6.167 MHz for high-frequency PLL mode.
CEPT—2.048 MHz for low-frequency PLL mode.
CEPT—8.192 MHz for high-frequency PLL mode.
Second Pulse.
A one-second timer with an active-high pulse. The duration
of the pulse is one RLCK cycle. Used for performance monitoring.
Ground.
Reset (Active-Low).
Asserting this pin low for at least 2.5 ms will reset the
entire device; this includes all internal counters and control registers.
Ready_Data Transfer Acknowledge.
In the Intel interface mode, this pin is
asserted high to indicate the completion of a read or write access; this pin is
forced into a high-impedance state while CS is high.
In the Motorola interface mode, this pin is asserted low to indicate the com-
pletion of a read or write access; this pin is forced to a 1 state otherwise.
5 V Supply.
Interrupt.
INT is asserted high, indicating an internal interrupt condition/
event has been generated. Otherwise, INT is in the 0 state. Interrupt events/
conditions are maskable through the control registers.
Chip Select_Address Strobe (Active-Low).
In the Intel interface mode,
this pin must be asserted low to initiate a read or write access and kept low
for the duration of the access; asserting CS low forces RDY from its high-
impedance state into a 0 state.
In the Motorola interface mode, this pin must be asserted low to initiate a
read or write access and kept low for the duration of the access.
21
EPLL
O
22
DPLLCK
O
23
DCLKXR
O
24
PLLCK
I
25
SEC
O
26
27
V
SS
RESET
—
I
u
28
RDY_DTACK
O
29
30
V
DD
INT
—
O
31
CS_AS
—
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相關代理商/技術參數
參數描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關 ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關 ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風格: 端子密封: 觸點電鍍: 照明:
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