參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 21/110頁
文件大小： 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
17
Lucent Technologies Inc.
Pin Information
(continued)
Table 2. Pin Descriptions for the 80-Pin Package
1. I
u
indicates an internal pull-up.
Pin
1
2
3
4
Symbol
TEST0
TEST1
FRMMOD
MPI
Type
1
I
u
I
u
I
u
I
u
Name and Function
TEST 0 (Active-Low). Manufacture Testing Only.
TEST 1 (Active-Low). Manufacture Testing Only.
Framer Mode.
Strap this pin to Vss (GROUND) to enable the framer mode.
Microprocessor Interface.
Strap to V
DD
to enable the Intel 80X86/88 proto-
col. Strap to V
SS
to enable the Motorola 680X0 protocol.
5 V Supply.
3-State (Active-Low).
Asserting this pin low forces all outputs into a high-
impedance state.
Transmit Signaling Superframe Reset (Active-Low).
Assert this pin low
to reset the DS1 signaling superframe counter and force a new signaling
superframe structure.
Ground.
No Connect.
Receive Signaling Superframe Sync.
A 3 ms interval in DS1. A 2 ms inter-
val in ITU-CEPT. Sourced from the CHI, this is an 8-bit wide pulse; sourced
from the framer, this is a 1-bit wide pulse.
Transmit Signaling Superframe Sync.
A 3 ms interval in DS1. A 2 ms
interval in ITU-CEPT. Sourced from the CHI, this is an 8-bit wide pulse;
sourced from the framer, this is a 1-bit wide pulse.
No Connect.
Receive CRC Error.
Indication of a receive checksum error. In ESF, this pin
is asserted at the onset of the CRC-6 error and remains asserted for the
duration of the extended superframe. In CEPT, this pin is asserted once for
the errored checksum block for a 1-byte interval.
Error Phase-Lock Loop Signal.
The error signal proportional to the phase
difference between DCLKXR and DPLLCK as detected from the internal
PLL circuitry.
No Connect.
Divided-Down Phase-Lock Loop Clock.
32 kHz or 8 kHz clock signal
derived from the PLLCK input signal.
Divided-Down CHI Clock.
32 kHz or 8 kHz clock signal derived from the
CLKXR input signal.
Phase-Lock Loop Clock.
This clock signal is used to clock the transmit
framer. This signal should be phase-locked to the CLKXR clock signal.
DS1—1.544 MHz for low-frequency PLL mode.
DS1—6.167 MHz for high-frequency PLL mode.
CEPT—2.048 MHz for low-frequency PLL mode.
CEPT—8.192 MHz for high-frequency PLL mode.
Second Pulse.
A one-second timer with an active-high pulse. The duration
of the pulse is one RLCK cycle. Used for performance monitoring.
5
6
V
DD
—
I
u
3-STATE
7
XSFRST
I
u
8
9
10
V
SS
NC
—
—
O
RSFSYN
12
TSFSYN
O
13
14
NC
CER
—
O
15
EPLL
O
16
17
NC
—
O
DPLLCK
18
DCLKXR
O
19
PLLCK
I
20
SEC
O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明:
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