參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 10/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
6
Lucent Technologies Inc.
List of Tables
(continued)
Tables
Page
Table 51. Receive Sa-Bit Register (SR21) ............................................................................................................ 78
Table 52. Receive Sa-Bit and X-Bit Register (SR22) ............................................................................................ 78
Table 53. Received Signaling Registers: DS1 Format (RSR0—RSR23) .............................................................. 79
Table 54. Receive Signaling Registers: CEPT Format (RSR0—RSR31) ............................................................. 79
Table 55. Primary Interrupt Group Enable Register (PR0) .................................................................................... 80
Table 56. Framer Mode Option Bits Decoding ...................................................................................................... 81
Table 57. Automatic Transmission Enable Register (PR2) ................................................................................... 82
Table 58. On-Demand Register 1 Bits Decoding .................................................................................................. 82
Table 59. On-Demand Register 2 Bits Decoding .................................................................................................. 83
Table 60. Framer System Squelch Code Register (PR5) ...................................................................................... 84
Table 61. Sa4—Sa8 Source Register (PR6) ......................................................................................................... 84
Table 62. Si-Bit/X-Bit/E-Bit Source Register (PR7) ............................................................................................... 85
Table 63. Framer Exercise Register (PR8) ........................................................................................................... 85
Table 64. Framer Exercises, PR8, Bits 5—0 ......................................................................................................... 86
Table 65. Facility Alarm Interrupt Enable Register (PR9) ...................................................................................... 88
Table 66. Signaling Mode Register (PR10) ........................................................................................................... 89
Table 67. System Clock Control Register (PR11) ................................................................................................. 90
Table 68. Framer Line Idle Code Register (PR12) ................................................................................................ 91
Table 69. CHI Common Control Register (PR13) ................................................................................................. 91
Table 70. CHI Transmit Control Register (PR14) .................................................................................................. 91
Table 71. CHI Receive Control Register (PR15) ................................................................................................... 92
Table 72. CHI Transmit Time-Slot Enable Registers (PR16—PR19) .................................................................... 92
Table 73. Receive Time-Slot Enable Registers (PR20—PR23) ............................................................................ 92
Table 74. CHI Transmit Highway Select Registers (PR24—PR27) ...................................................................... 93
Table 75. CHI Receive Highway Select Registers (PR28—PR31) ....................................................................... 93
Table 76. Transmit Signaling Registers: DS1 Format (TSR0—TSR23) ................................................................ 93
Table 77. Transmit Signaling Registers: CEPT Format (TSR0—TSR31) ............................................................. 94
Table 78. Status Register Map .............................................................................................................................. 95
Table 79. Receive Signaling Registers MAP ......................................................................................................... 96
Table 80. Parameter Registers MAP ..................................................................................................................... 97
Table 81. Transmit Signaling Registers MAP ........................................................................................................ 98
Table 82. ESD Threshold Voltage ......................................................................................................................... 99
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點電鍍: 照明:
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