參數(shù)資料
型號： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 22/110頁
文件大小： 752K
代理商： T7230A
Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
18
Lucent Technologies Inc.
Pin Information
(continued)
Table 2. Pin Descriptions for the 80-Pin Package
(continued)
1. I
u
indicates an internal pull-up.
Pin
21
22
Symbol
V
SS
RESET
Type
1
—
I
u
Name and Function
Ground.
Reset (Active-Low).
Asserting this pin low for at least 2.5 ms will reset the
entire device, this includes all internal counters and control registers.
Ready_Data Transfer Acknowledge.
In the Intel interface mode, this pin is
asserted high to indicate the completion of a read or write access; this pin is
forced into a high-impedance state while CS is high.
In the Motorola interface mode, this pin is asserted low to indicate the com-
pletion of a read or write access; this pin is forced to a 1 state otherwise.
5 V Supply.
Interrupt.
INT is asserted high indicating an internal interrupt condition/
event has been generated. Otherwise, INT is in the 0 state. Interrupt events/
conditions are maskable through the control registers.
Chip Select_Address Strobe (Active-Low).
In the Intel interface mode,
this pin must be asserted low to initiate a read or write access and kept low
for the duration of the access; asserting CS low forces RDY from its high-
impedance state into a 0 state.
In the Motorola interface mode, this pin must be asserted low to initiate a
read or write access and kept low for the duration of the access.
Read_Read/Write.
While RD is low in the Intel interface mode, the T7230A
drives the data bus with the contents of the addressed register.
In the Motorola interface mode, this signal is asserted high for read
accesses or asserted low for write accesses.
Write_Data Strobe (Active-Low).
In the Intel mode, the value present on
the data bus is latched into the addressed register on the positive edge of
the signal applied to WR. In the Motorola mode, when AS = 0 and R/W = 0
(write), the value present on the data bus is latched into internal flip-flops on
the positive edge of the signal applied to DS; when AS = 0 and R/W = 1
(read), the T7230A drives the data bus with the contents of the addressed
register while DS = 0.
Microprocessor Data Bus.
Bidirectional data bus used for read and write
accesses. While the T7230A is not driving the data bus, the T7230A will
force these pin into a high-impedance state.
No Connect.
Ground.
Microprocessor Clock.
16 MHz microprocessor clock. Used only for timing
the internal RDY signal.
Microprocessor Address Bus.
Address bus used to access internal regis-
ters.
No Connect.
5 V Supply.
23
RDY_DTACK
O
24
25
V
DD
INT
—
O
26
CS_AS
—
27
RD_R/W
I
28
WR_DS
I
29—36
D7—D0
I/O
37
38
39
NC
V
SS
MPCK
—
—
I
40—44
46—47
45
48
A6—A0
I
NC
V
DD
—
—
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
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T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
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