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參數(shù)資料
| 型號(hào)： | T7230A |
| 廠商： | Lineage Power |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 84/110頁(yè) |
| 文件大?。?/td> | 752K |
| 代理商： | T7230A |
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Preliminary Data Sheet
T7230A Primary Access Framer/Controller
June 1997
80
Lucent Technologies Inc.
Register Structure
(continued)
Parameter/Control Registers
These registers define the mode configuration of each framer unit, are initially set to a default value upon a hard-
ware reset, and are all read/write registers.
Default states of all bits in this register group are also indicated in the parameter/control register map.
Primary Interrupt Group Enable Register (PR0)
The bits in this register enable the event groups that assert the interrupt pin high.
Table 55. Primary Interrupt Group Enable Register (PR0)
Bits
0
1
2
3
4
Description
Facility Alarm Interrupt Enable (FAIE).
A 1 enables facility alarm interrupts.
Remote Alarm Interrupt Enable (RAIE).
A 1 enables remote alarm interrupts.
Facility Event Interrupt Enable (FEIE).
A 1 enables facility event interrupts.
System Event Interrupt Enable (SEIE).
A 1 enables system event interrupts.
Transmit Signaling Superframe Event Interrupt Enable (TSSEI).
A 1 enables an interrupt at the start
of a transmit line signaling superframe.
Receive Signaling Superframe Event Interrupt Enable (RSSEI).
A 1 enables an interrupt at the start
of a receive line signaling superframe.
Excessive CRC Error Interrupt Enable (ECEIE).
A 1 enables interrupts whenever the receive framer
detects excessive CRC errors. The threshold is 32 out of 33 errored CRC checksum blocks for ESF and
915 out of 1000 for CEPT.
Master Interrupt Enable (MIE).
A 1 permits enabled interrupt conditions to generate interrupts. A 0 will
disable
all
interrupts.
5
6
7
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| T7-231A1 | 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明: |
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