參數(shù)資料
型號(hào)： T7230A
廠商： Lineage Power
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 23/110頁
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
19
Lucent Technologies Inc.
Pin Information
(continued)
Table 2. Pin Descriptions for the 80-Pin Package
(continued)
1. I
u
indicates an internal pull-up.
Pin
49
Symbol
TSCB_TID
Type
1
I/O
Name and Function
CHI Time-Slot Control for Port B.
The T7230A drives this pin low to enable
external bus drivers for active CHI time slots.
TID.
In the framer mode (FRMMOD = 0), this is the input data signal for the
transmit framer.
Receive CHI Data Port B.
Serial input system data at 2.048 Mbits/s or
4.096 Mbits/s.
Buffer Overflow.
In framer mode (FRMMOD = 0), this may be used in per-
formance monitoring to indicate an overflow event from an external elastic
store.
No Connect.
Transmit CHI Data Port B.
Serial output system data at 2.048 Mbits/s or
4.096 Mbits/s. This port is forced into a high-impedance state for all inactive
time slots.
Receive Signaling Inhibit.
In framer mode (FRMMOD = 0), this pin is
forced to a 1 state for the duration of a loss of frame, loss of superframe
(DS1), or loss of time slot 16 multiframe (CEPT) alignment state.
Framer Receive Line Clock.
Framer receive line clock used in the receive
framer section, derived from RLCK (same phase).
CHI Time-Slot Control for Port A (Active-Low).
The T7230A drives this pin
low to enable external bus drivers for active CHI time slots.
No Connect.
Receive CHI Data Port A.
Serial input system data at 2.048 Mbits/s or
4.096 Mbits/s.
Buffer Underflow.
In framer mode (FRMMOD = 0), this may be used in per-
formance monitoring to indicate an underflow event from an external elastic
store.
Transmit CHI Data Port A.
Serial output system data at 2.048 Mbits/s or
4.096 Mbits/s. This port is forced into a high-impedance state for all inactive
time slots.
Receive Data.
In framer mode (FRMMOD = 0), this is the serial unirail out-
put data from the receive framer at 1.544 Mbits/s (DS1) or 2.048 Mbits/s
(CEPT) rates.
Output CHI Frame Sync.
In the CHI master mode, the T7230A’s receive
CHI circuit generates an 8 kHz frame sync on this pin for use on the CHI.
Ground.
No Connect.
CHI Frame Sync.
8 kHz frame sync from a CHI master.
CHI Transmit/Receive Clock.
2.048/4.096/8.192 MHz CHI clock signal. The
PLLCK signal should be phase-locked to CLKXR.
Divided-Down Receive Line Clock.
8 kHz clock signal derived from the
RLCK input signal.
50
DRB_BOF_CLKX
I
51
52
NC
—
O
DXB_RSI
54
FRMRCLK
O
55
TSCA
O
56
57
NC
—
I
DRA_BUF
58
DXA_RD
O
59
OFS
O
60
61
62
63
V
SS
NC
FS
CLKXR
—
—
I
I
64
DRLCK
O
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動(dòng)開關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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