參數(shù)資料
型號(hào)： T7230A
廠商： Lineage Power
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 65/110頁(yè)
文件大?。?/td> 752K
代理商： T7230A
Preliminary Data Sheet
June 1997
T7230A Primary Access Framer/Controller
61
Lucent Technologies Inc.
Concentration Highway Interface (CHI)
T7230A uses a dual, high-speed, serial interface known as the CHI on the system side. This interface is a very flex-
ible, high-speed bus. Configured via the highway control registers (PR13—PR31), this interface can be set up in a
number of different configurations.
The following is a list of the CHI features:
1. AT&T standard interface for communication devices.
2. Two pairs of transmit and receive paths to carry data in 8-bit time slots.
3. Programmable definition of highways through offset and clock-edge options (independent for transmit and
receive directions).
4. Programmable activation of each receive time slot.
5. Programmable 3-state of each transmit time slot.
6. An 8 kHz framing signal to synchronize each direction of data flow.
7. A device generated, receive line clock derived, 8 kHz frame synchronization signal.
8. Compatible with Mitel
1
and AMD
2
PCM highways.
9. Compatible with the GCI specification.
The concentration highway interface consists of the following signals:
1. CLKXR = User-supplied clock signal.
2. FS = CHI frame synchronization (FS) signal (8 kHz). All system receive and transmit time slots are referenced
from the FS signal.
3. OFS = T7230A generated CHI frame synchronization (OFS) signal (8 kHz); this output is enabled by
programming the CHIMM to 1.
4. DRA, DRB = Receive CHI data from the system.
5. DXA, DXB = Transmit CHI data to the system.
6. TSCA, TSCB = Time-slot control signals (can be used to enable optional external buffers to drive the DXA or
DXB output lines).
Rate adaptation is required for all DS1 formats between the 1.544 Mbits/s line rate and 2.048 Mbits/s (or
4.096 Mbits/s) CHI rate. This is achieved by means of stuffing eight idle time slots
3
into the existing 24 time slots of
the T1 frame. Idle time slots are transmitted every fourth time slot (starting in the first, second, third, or fourth time
slot) or grouped together at the end of the CHI frame (default setting). The positioning of the idle time slots is the
same for transmit and receive directions. Idle time slots contain a programmable code. Idle or unused time slots
can be disabled (the DX interface is forced to a high-impedance state for the interval of the unused time slot).
Supported also is an associated signaling mode in which the CHI carries data and its associated signaling informa-
tion within a 16-bit time slot.
1. Mitel is a registered trademark of Mitel Corporation.
2. AMD is a registered trademark of Advanced Micro Devices, Inc.
3. These stuffed time slots are ignored on the received CHI and are forced to a high-impedance state in the transmit CHI.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T-7230A--ML 制造商:Rochester Electronics LLC 功能描述:- Bulk
T7230-ML3 制造商:AGERE 功能描述:
T7-231A1 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard Bat Handle RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類(lèi)型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
T7-231A2 制造商:OTTO Engineering Inc 功能描述:2POLE, SOLDER, STD,
T7-231A2D 功能描述:撥動(dòng)開(kāi)關(guān) ON NONE OFF 2 Pole Standard LeverLock RoHS:否 制造商:OTTO 觸點(diǎn)形式: 開(kāi)關(guān)功能: 電流額定值: 電壓額定值 AC: 電壓額定值 DC: 功率額定值: 端接類(lèi)型: 安裝風(fēng)格: 端子密封: 觸點(diǎn)電鍍: 照明:
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